--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: K.39
--  \   \         Application: netgen
--  /   /         Filename: I2CmasterDemo_timesim.vhd
-- /___/   /\     Timestamp: Fri Jan 22 01:36:39 2010
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 4 -pcf I2CmasterDemo.pcf -rpw 100 -tpw 0 -ar Structure -tm I2CmasterDemo -insert_pp_buffers false -w -dir netgen/par -ofmt vhdl -sim I2CmasterDemo.ncd I2CmasterDemo_timesim.vhd 
-- Device	: 3s250epq208-4 (PRODUCTION 1.27 2008-01-09)
-- Input file	: I2CmasterDemo.ncd
-- Output file	: C:\Documents and Settings\sxs5464\Desktop\RapidFPGA\code\Xilinx Projects\ImagerController\netgen\par\I2CmasterDemo_timesim.vhd
-- # of Entities	: 1
-- Design Name	: I2CmasterDemo
-- Xilinx	: C:\Xilinx\10.1\ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity I2CmasterDemo_par is
  port (
    I2C_Data : inout STD_LOGIC; 
    I2C_Clk : out STD_LOGIC; 
    FPGA_Clk : in STD_LOGIC := 'X'; 
    SW : in STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end I2CmasterDemo_par;

architecture Structure of I2CmasterDemo_par is
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_6_Q : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_1_Q : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_3_Q : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_5_Q : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_7_Q : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_1_Q : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_3_Q : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_5_Q : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_7_Q : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_9_Q : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_11_Q : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_4_Q : STD_LOGIC; 
  signal N91_0 : STD_LOGIC; 
  signal FPGA_Clk_BUFGP : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq0000_0 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_1_Q : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_3_Q : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q : STD_LOGIC; 
  signal UUT_Dir_2438 : STD_LOGIC; 
  signal UUT_out_i2c : STD_LOGIC; 
  signal SW_0_IBUF_2440 : STD_LOGIC; 
  signal SW_1_IBUF_2441 : STD_LOGIC; 
  signal SW_2_IBUF_2442 : STD_LOGIC; 
  signal SW_3_IBUF_2443 : STD_LOGIC; 
  signal UUT_out_i2cclk_2445 : STD_LOGIC; 
  signal UUT_nstate_FFd2_2446 : STD_LOGIC; 
  signal UUT_nstate_FFd1_2447 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not000181 : STD_LOGIC; 
  signal UUT_N32_0 : STD_LOGIC; 
  signal UUT_nstate_FFd3_2450 : STD_LOGIC; 
  signal UUT_N13_0 : STD_LOGIC; 
  signal N25_0 : STD_LOGIC; 
  signal UUT_N65_0 : STD_LOGIC; 
  signal UUT_nstate_FFd4_2454 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0001_0 : STD_LOGIC; 
  signal UUT_Madd_counter_addsub0000_cy_2_0 : STD_LOGIC; 
  signal UUT_N112_0 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0010 : STD_LOGIC; 
  signal UUT_ClkRisingEdge_2465 : STD_LOGIC; 
  signal CLK_sI2C_Clk_2469 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In37 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_240_2471 : STD_LOGIC; 
  signal UUT_N26_0 : STD_LOGIC; 
  signal UUT_N62_0 : STD_LOGIC; 
  signal N103 : STD_LOGIC; 
  signal N106 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux0000231_O : STD_LOGIC; 
  signal UUT_shiftReg_and0000_0 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0002_0 : STD_LOGIC; 
  signal N33_0 : STD_LOGIC; 
  signal UUT_Dir_mux000011_SW0_O : STD_LOGIC; 
  signal UUT_Dir_mux000011_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000078_0 : STD_LOGIC; 
  signal UUT_N33_2487 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000091_O : STD_LOGIC; 
  signal UUT_N45 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000094_0 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0000_0 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_115_SW0_O : STD_LOGIC; 
  signal N35_0 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_115_0 : STD_LOGIC; 
  signal UUT_N69_0 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_1175_2496 : STD_LOGIC; 
  signal N114_0 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_1129_2498 : STD_LOGIC; 
  signal N98_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_cmp_eq00001_SW0_O : STD_LOGIC; 
  signal UUT_N41 : STD_LOGIC; 
  signal UUT_N53_0 : STD_LOGIC; 
  signal UUT_N50_0 : STD_LOGIC; 
  signal N42_0 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_1178_SW1_SW0_O : STD_LOGIC; 
  signal N43_0 : STD_LOGIC; 
  signal N56_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not0001_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux0000119_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000065_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000034_O : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0006_0 : STD_LOGIC; 
  signal N128_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_cmp_eq0000 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_2515 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0011 : STD_LOGIC; 
  signal UUT_N3178_0 : STD_LOGIC; 
  signal UUT_N349_0 : STD_LOGIC; 
  signal UUT_N362_2519 : STD_LOGIC; 
  signal UUT_N3_0 : STD_LOGIC; 
  signal UUT_Dir_mux0000108_O : STD_LOGIC; 
  signal UUT_Dir_mux0000121_0 : STD_LOGIC; 
  signal UUT_N3157_SW0_O : STD_LOGIC; 
  signal UUT_N3157_0 : STD_LOGIC; 
  signal UUT_N392_0 : STD_LOGIC; 
  signal UUT_N3106_O : STD_LOGIC; 
  signal N119_0 : STD_LOGIC; 
  signal UUT_N60 : STD_LOGIC; 
  signal UUT_Dir_mux0000611_SW0_O : STD_LOGIC; 
  signal UUT_Dir_mux000058_0 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux00002_SW0_SW0_O : STD_LOGIC; 
  signal N51_0 : STD_LOGIC; 
  signal N53 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq00031_SW1_O : STD_LOGIC; 
  signal UUT_nstate_FFd3_In_SW0_O : STD_LOGIC; 
  signal N13_0 : STD_LOGIC; 
  signal UUT_shiftReg_or0000 : STD_LOGIC; 
  signal UUT_shiftReg_or000032_0 : STD_LOGIC; 
  signal UUT_shiftReg_or000017_0 : STD_LOGIC; 
  signal UUT_N331_0 : STD_LOGIC; 
  signal UUT_N31_0 : STD_LOGIC; 
  signal N153_0 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_18_O : STD_LOGIC; 
  signal UUT_ack_count_cmp_eq0003 : STD_LOGIC; 
  signal UUT_N211_0 : STD_LOGIC; 
  signal UUT_shiftReg_or00002_SW0_O : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000026_SW0_O : STD_LOGIC; 
  signal UUT_N511 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000026_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not000111_O : STD_LOGIC; 
  signal N116_0 : STD_LOGIC; 
  signal N126_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not000141_0 : STD_LOGIC; 
  signal UUT_N57 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000047_0 : STD_LOGIC; 
  signal UUT_N27 : STD_LOGIC; 
  signal N22_0 : STD_LOGIC; 
  signal UUT_N351_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000066_0 : STD_LOGIC; 
  signal N159_0 : STD_LOGIC; 
  signal N181_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000097_0 : STD_LOGIC; 
  signal UUT_ClkFallingEdge_2566 : STD_LOGIC; 
  signal UUT_N64 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0008 : STD_LOGIC; 
  signal UUT_Dir_mux0000169_0 : STD_LOGIC; 
  signal UUT_Dir_mux000082_0 : STD_LOGIC; 
  signal UUT_Dir_mux0000194_SW1_O : STD_LOGIC; 
  signal UUT_delay_count_or0000 : STD_LOGIC; 
  signal N134_0 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_1155_0 : STD_LOGIC; 
  signal UUT_ack_count_and0025 : STD_LOGIC; 
  signal UUT_N67_0 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_10_23_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_114_0 : STD_LOGIC; 
  signal N146_0 : STD_LOGIC; 
  signal N49 : STD_LOGIC; 
  signal N96_0 : STD_LOGIC; 
  signal UUT_N11 : STD_LOGIC; 
  signal UUT_N35 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux000055_0 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux000061_SW0_O : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux000061_0 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux000041_0 : STD_LOGIC; 
  signal N69_0 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_43_O : STD_LOGIC; 
  signal UUT_Dir_mux00012_SW0_O : STD_LOGIC; 
  signal UUT_ack_count_mux0000_10_25_SW0_O : STD_LOGIC; 
  signal UUT_N14_0 : STD_LOGIC; 
  signal UUT_N33_O : STD_LOGIC; 
  signal UUT_N320_0 : STD_LOGIC; 
  signal UUT_N327_0 : STD_LOGIC; 
  signal UUT_nstate_FFd1_1_2596 : STD_LOGIC; 
  signal UUT_nstate_FFd4_1_2597 : STD_LOGIC; 
  signal UUT_nstate_FFd3_1_2598 : STD_LOGIC; 
  signal UUT_nstate_FFd2_1_2599 : STD_LOGIC; 
  signal UUT_N392_SW0_O : STD_LOGIC; 
  signal UUT_shiftReg_or000012_O : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0012_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_131_O : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_110_0 : STD_LOGIC; 
  signal N71_0 : STD_LOGIC; 
  signal UUT_N38_0 : STD_LOGIC; 
  signal N86_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_119_SW1_O : STD_LOGIC; 
  signal UUT_N0_0 : STD_LOGIC; 
  signal N58_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_216_0 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux0000133_0 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux00009_O : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_2614 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux0000113_O : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000053_O : STD_LOGIC; 
  signal UUT_out_i2cclk_mux00002_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not00012_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not0001168_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not0001125_O : STD_LOGIC; 
  signal N157_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000118_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000131_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000163_O : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000162_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000176_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not0001168_SW0_O : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0000_SW0_O : STD_LOGIC; 
  signal UUT_N12 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_25_0 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0005_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_1_SW0_O : STD_LOGIC; 
  signal N105_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_5_O : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_3_5_O : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_5_SW0_O : STD_LOGIC; 
  signal N102_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_6_3_O : STD_LOGIC; 
  signal N78_0 : STD_LOGIC; 
  signal N77_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_119_O : STD_LOGIC; 
  signal UUT_counter_mux0000_4_1_SW0_O : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000027_SW0_SW0_O : STD_LOGIC; 
  signal N123_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_111_SW1_O : STD_LOGIC; 
  signal UUT_delay_count_mux0000_11_1_SW1_O : STD_LOGIC; 
  signal UUT_delay_count_and0000_0 : STD_LOGIC; 
  signal UUT_N15_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000216_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000204_O : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq00031_SW2_O : STD_LOGIC; 
  signal UUT_nstate_FFd4_In0_0 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In77_O : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_18_SW0_O : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_0_0 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_181_O : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_117_0 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_146_O : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_122_0 : STD_LOGIC; 
  signal UUT_N4_0 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000054_0 : STD_LOGIC; 
  signal UUT_prevClk_2675 : STD_LOGIC; 
  signal N39_0 : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq00007_0 : STD_LOGIC; 
  signal UUT_Dir_mux0000148_0 : STD_LOGIC; 
  signal UUT_Dir_mux0000143_2682 : STD_LOGIC; 
  signal N169 : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq000016_2684 : STD_LOGIC; 
  signal N183 : STD_LOGIC; 
  signal N95_0 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_XORF_3563 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYINIT_3562 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_F : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_XORG_3551 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_8_Q : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYSELF_3549 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYMUXFAST_3548 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYAND_3547 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_FASTCARRY_3546 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYMUXG2_3545 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYMUXF2_3544 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_LOGIC_ZERO_3543 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYSELG_3534 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_G : STD_LOGIC; 
  signal UUT_ack_count_share0000_10_XORF_3594 : STD_LOGIC; 
  signal UUT_ack_count_share0000_10_LOGIC_ZERO_3593 : STD_LOGIC; 
  signal UUT_ack_count_share0000_10_CYINIT_3592 : STD_LOGIC; 
  signal UUT_ack_count_share0000_10_CYSELF_3583 : STD_LOGIC; 
  signal UUT_ack_count_share0000_10_F : STD_LOGIC; 
  signal UUT_ack_count_share0000_10_XORG_3580 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_10_Q : STD_LOGIC; 
  signal UUT_ack_count_11_rt_3577 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ZERO_3625 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYINIT_3624 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELF_3618 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut_0_1_3617 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYMUXG_3615 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_0_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ONE_3613 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELG_3605 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut_1_1_3604 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut_2_1_3650 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELF_3649 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXFAST_3648 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYAND_3647 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_FASTCARRY_3646 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXG2_3645 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXF2_3644 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3643 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELG_3635 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut_3_1_3634 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_1_CYINIT_3684 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELF_3677 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_1_CYMUXG_3674 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_1_LOGIC_ZERO_3672 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELG_3666 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELF_3708 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXFAST_3707 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_CYAND_3706 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_FASTCARRY_3705 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXG2_3704 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXF2_3703 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_LOGIC_ZERO_3702 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELG_3696 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELF_3738 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXFAST_3737 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_CYAND_3736 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_FASTCARRY_3735 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXG2_3734 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXF2_3733 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_LOGIC_ZERO_3732 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELG_3726 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_CYSELF_3768 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_CYMUXFAST_3767 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_CYAND_3766 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_FASTCARRY_3765 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_CYMUXG2_3764 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_CYMUXF2_3763 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_LOGIC_ZERO_3762 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_CYSELG_3756 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_XORF_3809 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_LOGIC_ONE_3808 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_CYINIT_3807 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_CYSELF_3798 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_XORG_3794 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_CYMUXG_3793 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_0_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_LOGIC_ZERO_3791 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_CYSELG_3782 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_XORF_3847 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYINIT_3846 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_XORG_3835 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_2_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYSELF_3833 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYMUXFAST_3832 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYAND_3831 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_FASTCARRY_3830 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYMUXG2_3829 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYMUXF2_3828 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_LOGIC_ZERO_3827 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYSELG_3818 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_XORF_3253 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYINIT_3252 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_XORG_3241 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYSELF_3239 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYMUXFAST_3238 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYAND_3237 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_FASTCARRY_3236 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYMUXG2_3235 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYMUXF2_3234 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_LOGIC_ZERO_3233 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYSELG_3224 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_30_XORF_3268 : STD_LOGIC; 
  signal UUT_writeCount_share0000_30_CYINIT_3267 : STD_LOGIC; 
  signal UUT_writeCount_30_rt_3265 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ZERO_3299 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYINIT_3298 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELF_3289 : STD_LOGIC; 
  signal UUT_delay_count_2_rt_3288 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYMUXG_3286 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_0_Q : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ONE_3284 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELG_3276 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_1_Q_3275 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ZERO_3330 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_2_Q_3322 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELF_3321 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXFAST_3320 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYAND_3319 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_FASTCARRY_3318 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXG2_3317 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXF2_3316 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ONE_3315 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELG_3306 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_3_Q : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ZERO_3361 : STD_LOGIC; 
  signal UUT_delay_count_8_rt_3352 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELF_3351 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXFAST_3350 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYAND_3349 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_FASTCARRY_3348 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXG2_3347 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXF2_3346 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ONE_3345 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELG_3339 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_5_Q_3338 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_6_LOGIC_ONE_3376 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYINIT_3375 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYSELF_3368 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_6_Q_3367 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_XORF_3411 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_LOGIC_ONE_3410 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_CYINIT_3409 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_CYSELF_3400 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_XORG_3396 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_CYMUXG_3395 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_0_Q : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_LOGIC_ZERO_3393 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_CYSELG_3384 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_G : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_XORF_3449 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYINIT_3448 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_F : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_XORG_3437 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_2_Q : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYSELF_3435 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYMUXFAST_3434 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYAND_3433 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_FASTCARRY_3432 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYMUXG2_3431 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYMUXF2_3430 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_LOGIC_ZERO_3429 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYSELG_3420 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_G : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_XORF_3487 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYINIT_3486 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_F : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_XORG_3475 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_4_Q : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYSELF_3473 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYMUXFAST_3472 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYAND_3471 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_FASTCARRY_3470 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYMUXG2_3469 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYMUXF2_3468 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_LOGIC_ZERO_3467 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYSELG_3458 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_G : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_XORF_3525 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYINIT_3524 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_F : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_XORG_3513 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_6_Q : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYSELF_3511 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYMUXFAST_3510 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYAND_3509 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_FASTCARRY_3508 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYMUXG2_3507 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYMUXF2_3506 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_LOGIC_ZERO_3505 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYSELG_3496 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_XORF_2911 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYINIT_2910 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_XORG_2899 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYSELF_2897 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYMUXFAST_2896 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYAND_2895 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_FASTCARRY_2894 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYMUXG2_2893 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYMUXF2_2892 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_LOGIC_ZERO_2891 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYSELG_2882 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_XORF_2949 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYINIT_2948 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_XORG_2937 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYSELF_2935 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYMUXFAST_2934 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYAND_2933 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_FASTCARRY_2932 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYMUXG2_2931 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYMUXF2_2930 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_LOGIC_ZERO_2929 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYSELG_2920 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_XORF_2987 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYINIT_2986 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_XORG_2975 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYSELF_2973 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYMUXFAST_2972 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYAND_2971 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_FASTCARRY_2970 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYMUXG2_2969 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYMUXF2_2968 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_LOGIC_ZERO_2967 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYSELG_2958 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_XORF_3025 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYINIT_3024 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_XORG_3013 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYSELF_3011 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYMUXFAST_3010 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYAND_3009 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_FASTCARRY_3008 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYMUXG2_3007 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYMUXF2_3006 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_LOGIC_ZERO_3005 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYSELG_2996 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_XORF_3063 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYINIT_3062 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_XORG_3051 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYSELF_3049 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYMUXFAST_3048 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYAND_3047 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_FASTCARRY_3046 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYMUXG2_3045 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYMUXF2_3044 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_LOGIC_ZERO_3043 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYSELG_3034 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_XORF_3101 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYINIT_3100 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_XORG_3089 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYSELF_3087 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYMUXFAST_3086 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYAND_3085 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_FASTCARRY_3084 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYMUXG2_3083 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYMUXF2_3082 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_LOGIC_ZERO_3081 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYSELG_3072 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_XORF_3139 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYINIT_3138 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_XORG_3127 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYSELF_3125 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYMUXFAST_3124 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYAND_3123 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_FASTCARRY_3122 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYMUXG2_3121 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYMUXF2_3120 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_LOGIC_ZERO_3119 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYSELG_3110 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_XORF_3177 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYINIT_3176 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_XORG_3165 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYSELF_3163 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYMUXFAST_3162 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYAND_3161 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_FASTCARRY_3160 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYMUXG2_3159 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYMUXF2_3158 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_LOGIC_ZERO_3157 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYSELG_3148 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_XORF_3215 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYINIT_3214 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_XORG_3203 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYSELF_3201 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYMUXFAST_3200 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYAND_3199 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_FASTCARRY_3198 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYMUXG2_3197 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYMUXF2_3196 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_LOGIC_ZERO_3195 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYSELG_3186 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_XORF_2721 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_LOGIC_ONE_2720 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_CYINIT_2719 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_CYSELF_2710 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_XORG_2706 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_CYMUXG_2705 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_LOGIC_ZERO_2703 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_CYSELG_2694 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_XORF_2759 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYINIT_2758 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_XORG_2747 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYSELF_2745 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYMUXFAST_2744 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYAND_2743 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_FASTCARRY_2742 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYMUXG2_2741 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYMUXF2_2740 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_LOGIC_ZERO_2739 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYSELG_2730 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_XORF_2797 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYINIT_2796 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_XORG_2785 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYSELF_2783 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYMUXFAST_2782 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYAND_2781 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_FASTCARRY_2780 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYMUXG2_2779 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYMUXF2_2778 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_LOGIC_ZERO_2777 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYSELG_2768 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_XORF_2835 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYINIT_2834 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_XORG_2823 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYSELF_2821 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYMUXFAST_2820 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYAND_2819 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_FASTCARRY_2818 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYMUXG2_2817 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYMUXF2_2816 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_LOGIC_ZERO_2815 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYSELG_2806 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_XORF_2873 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYINIT_2872 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_XORG_2861 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYSELF_2859 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYMUXFAST_2858 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYAND_2857 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_FASTCARRY_2856 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYMUXG2_2855 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYMUXF2_2854 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_LOGIC_ZERO_2853 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYSELG_2844 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_G : STD_LOGIC; 
  signal CLK_clk_div_0_DXMUX_4203 : STD_LOGIC; 
  signal CLK_clk_div_0_XORF_4201 : STD_LOGIC; 
  signal CLK_clk_div_0_LOGIC_ONE_4200 : STD_LOGIC; 
  signal CLK_clk_div_0_CYINIT_4199 : STD_LOGIC; 
  signal CLK_clk_div_0_CYSELF_4190 : STD_LOGIC; 
  signal CLK_clk_div_0_DYMUX_4183 : STD_LOGIC; 
  signal CLK_clk_div_0_XORG_4181 : STD_LOGIC; 
  signal CLK_clk_div_0_CYMUXG_4180 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_0_Q : STD_LOGIC; 
  signal CLK_clk_div_0_LOGIC_ZERO_4178 : STD_LOGIC; 
  signal CLK_clk_div_0_CYSELG_4169 : STD_LOGIC; 
  signal CLK_clk_div_0_G : STD_LOGIC; 
  signal CLK_clk_div_0_SRINV_4167 : STD_LOGIC; 
  signal CLK_clk_div_0_CLKINV_4166 : STD_LOGIC; 
  signal CLK_clk_div_2_DXMUX_4255 : STD_LOGIC; 
  signal CLK_clk_div_2_XORF_4253 : STD_LOGIC; 
  signal CLK_clk_div_2_CYINIT_4252 : STD_LOGIC; 
  signal CLK_clk_div_2_F : STD_LOGIC; 
  signal CLK_clk_div_2_DYMUX_4238 : STD_LOGIC; 
  signal CLK_clk_div_2_XORG_4236 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_2_Q : STD_LOGIC; 
  signal CLK_clk_div_2_CYSELF_4234 : STD_LOGIC; 
  signal CLK_clk_div_2_CYMUXFAST_4233 : STD_LOGIC; 
  signal CLK_clk_div_2_CYAND_4232 : STD_LOGIC; 
  signal CLK_clk_div_2_FASTCARRY_4231 : STD_LOGIC; 
  signal CLK_clk_div_2_CYMUXG2_4230 : STD_LOGIC; 
  signal CLK_clk_div_2_CYMUXF2_4229 : STD_LOGIC; 
  signal CLK_clk_div_2_LOGIC_ZERO_4228 : STD_LOGIC; 
  signal CLK_clk_div_2_CYSELG_4219 : STD_LOGIC; 
  signal CLK_clk_div_2_G : STD_LOGIC; 
  signal CLK_clk_div_2_SRINV_4217 : STD_LOGIC; 
  signal CLK_clk_div_2_CLKINV_4216 : STD_LOGIC; 
  signal CLK_clk_div_4_DXMUX_4307 : STD_LOGIC; 
  signal CLK_clk_div_4_XORF_4305 : STD_LOGIC; 
  signal CLK_clk_div_4_CYINIT_4304 : STD_LOGIC; 
  signal CLK_clk_div_4_F : STD_LOGIC; 
  signal CLK_clk_div_4_DYMUX_4290 : STD_LOGIC; 
  signal CLK_clk_div_4_XORG_4288 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_4_Q : STD_LOGIC; 
  signal CLK_clk_div_4_CYSELF_4286 : STD_LOGIC; 
  signal CLK_clk_div_4_CYMUXFAST_4285 : STD_LOGIC; 
  signal CLK_clk_div_4_CYAND_4284 : STD_LOGIC; 
  signal CLK_clk_div_4_FASTCARRY_4283 : STD_LOGIC; 
  signal CLK_clk_div_4_CYMUXG2_4282 : STD_LOGIC; 
  signal CLK_clk_div_4_CYMUXF2_4281 : STD_LOGIC; 
  signal CLK_clk_div_4_LOGIC_ZERO_4280 : STD_LOGIC; 
  signal CLK_clk_div_4_CYSELG_4271 : STD_LOGIC; 
  signal CLK_clk_div_4_G : STD_LOGIC; 
  signal CLK_clk_div_4_SRINV_4269 : STD_LOGIC; 
  signal CLK_clk_div_4_CLKINV_4268 : STD_LOGIC; 
  signal CLK_clk_div_6_DXMUX_4352 : STD_LOGIC; 
  signal CLK_clk_div_6_XORF_4350 : STD_LOGIC; 
  signal CLK_clk_div_6_LOGIC_ZERO_4349 : STD_LOGIC; 
  signal CLK_clk_div_6_CYINIT_4348 : STD_LOGIC; 
  signal CLK_clk_div_6_CYSELF_4339 : STD_LOGIC; 
  signal CLK_clk_div_6_F : STD_LOGIC; 
  signal CLK_clk_div_6_DYMUX_4333 : STD_LOGIC; 
  signal CLK_clk_div_6_XORG_4331 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_6_Q : STD_LOGIC; 
  signal CLK_clk_div_7_rt_4328 : STD_LOGIC; 
  signal CLK_clk_div_6_SRINV_4320 : STD_LOGIC; 
  signal CLK_clk_div_6_CLKINV_4319 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ZERO_4386 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYINIT_4385 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELF_4377 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut_0_1_4376 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYMUXG_4374 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_0_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ONE_4372 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELG_4363 : STD_LOGIC; 
  signal UUT_delay_count_4_rt : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ZERO_4417 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut_2_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELF_4407 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXFAST_4406 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYAND_4405 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_FASTCARRY_4404 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXG2_4403 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXF2_4402 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ONE_4401 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELG_4393 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ZERO_4448 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut_4_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELF_4438 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXFAST_4437 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYAND_4436 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_FASTCARRY_4435 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXG2_4434 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXF2_4433 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ONE_4432 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELG_4424 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut_5_1_4423 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELF_4472 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXFAST_4471 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYAND_4470 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_FASTCARRY_4469 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXG2_4468 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXF2_4467 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_LOGIC_ZERO_4466 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELG_4457 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ZERO_4508 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYINIT_4507 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELF_4500 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYMUXG_4497 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_0_Q : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ONE_4495 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELG_4487 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ZERO_4539 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELF_4529 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXFAST_4528 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYAND_4527 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_FASTCARRY_4526 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXG2_4525 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXF2_4524 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ONE_4523 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELG_4514 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_XORF_3885 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYINIT_3884 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_XORG_3873 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_4_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYSELF_3871 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYMUXFAST_3870 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYAND_3869 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_FASTCARRY_3868 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYMUXG2_3867 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYMUXF2_3866 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_LOGIC_ZERO_3865 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYSELG_3856 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_XORF_3923 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYINIT_3922 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_XORG_3911 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_6_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYSELF_3909 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYMUXFAST_3908 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYAND_3907 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_FASTCARRY_3906 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYMUXG2_3905 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYMUXF2_3904 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_LOGIC_ZERO_3903 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYSELG_3894 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_XORF_3961 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYINIT_3960 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_XORG_3949 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_8_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYSELF_3947 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYMUXFAST_3946 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYAND_3945 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_FASTCARRY_3944 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYMUXG2_3943 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYMUXF2_3942 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_LOGIC_ZERO_3941 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYSELG_3932 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_XORF_3999 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYINIT_3998 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_XORG_3987 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_10_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYSELF_3985 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYMUXFAST_3984 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYAND_3983 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_FASTCARRY_3982 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYMUXG2_3981 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYMUXF2_3980 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_LOGIC_ZERO_3979 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYSELG_3970 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_XORF_4037 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYINIT_4036 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_XORG_4025 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_12_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYSELF_4023 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYMUXFAST_4022 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYAND_4021 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_FASTCARRY_4020 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYMUXG2_4019 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYMUXF2_4018 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_LOGIC_ZERO_4017 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYSELG_4008 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_14_XORF_4068 : STD_LOGIC; 
  signal UUT_delay_count_share0000_14_LOGIC_ZERO_4067 : STD_LOGIC; 
  signal UUT_delay_count_share0000_14_CYINIT_4066 : STD_LOGIC; 
  signal UUT_delay_count_share0000_14_CYSELF_4057 : STD_LOGIC; 
  signal UUT_delay_count_share0000_14_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_14_XORG_4054 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_14_Q : STD_LOGIC; 
  signal UUT_delay_count_15_rt_4051 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ZERO_4099 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYINIT_4098 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELF_4089 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYMUXG_4086 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_0_Q : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ONE_4084 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELG_4076 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ZERO_4130 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELF_4120 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXFAST_4119 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYAND_4118 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_FASTCARRY_4117 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXG2_4116 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXF2_4115 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ONE_4114 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELG_4107 : STD_LOGIC; 
  signal N91_LOGIC_ZERO_4157 : STD_LOGIC; 
  signal N91_CYINIT_4156 : STD_LOGIC; 
  signal N91_CYSELF_4150 : STD_LOGIC; 
  signal N91 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELF_4563 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXFAST_4562 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYAND_4561 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_FASTCARRY_4560 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXG2_4559 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXF2_4558 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_LOGIC_ZERO_4557 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELG_4550 : STD_LOGIC; 
  signal I2C_Data_O : STD_LOGIC; 
  signal I2C_Data_T : STD_LOGIC; 
  signal I2C_Data_INBUF : STD_LOGIC; 
  signal SW_0_INBUF : STD_LOGIC; 
  signal SW_1_INBUF : STD_LOGIC; 
  signal SW_2_INBUF : STD_LOGIC; 
  signal SW_3_INBUF : STD_LOGIC; 
  signal FPGA_Clk_INBUF : STD_LOGIC; 
  signal I2C_Clk_O : STD_LOGIC; 
  signal FPGA_Clk_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal FPGA_Clk_BUFGP_BUFG_I0_INV : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not000181_F5MUX_4657 : STD_LOGIC; 
  signal N190 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not000181_BXINV_4650 : STD_LOGIC; 
  signal N189 : STD_LOGIC; 
  signal UUT_writeCount_0_DXMUX_4686 : STD_LOGIC; 
  signal UUT_writeCount_0_F5MUX_4684 : STD_LOGIC; 
  signal N198 : STD_LOGIC; 
  signal UUT_writeCount_0_BXINV_4677 : STD_LOGIC; 
  signal N197 : STD_LOGIC; 
  signal UUT_writeCount_0_CLKINV_4669 : STD_LOGIC; 
  signal UUT_nstate_FFd2_DXMUX_4720 : STD_LOGIC; 
  signal UUT_nstate_FFd2_FXMUX_4719 : STD_LOGIC; 
  signal UUT_nstate_FFd2_F5MUX_4718 : STD_LOGIC; 
  signal N143 : STD_LOGIC; 
  signal UUT_nstate_FFd2_BXINV_4711 : STD_LOGIC; 
  signal N142 : STD_LOGIC; 
  signal UUT_nstate_FFd2_SRINV_4703 : STD_LOGIC; 
  signal UUT_nstate_FFd2_CLKINV_4702 : STD_LOGIC; 
  signal UUT_nstate_FFd1_DXMUX_4755 : STD_LOGIC; 
  signal UUT_nstate_FFd1_FXMUX_4754 : STD_LOGIC; 
  signal UUT_nstate_FFd1_F5MUX_4753 : STD_LOGIC; 
  signal N200 : STD_LOGIC; 
  signal UUT_nstate_FFd1_BXINV_4746 : STD_LOGIC; 
  signal N199 : STD_LOGIC; 
  signal UUT_nstate_FFd1_SRINV_4738 : STD_LOGIC; 
  signal UUT_nstate_FFd1_CLKINV_4737 : STD_LOGIC; 
  signal UUT_counter_4_DXMUX_4787 : STD_LOGIC; 
  signal UUT_counter_4_F5MUX_4785 : STD_LOGIC; 
  signal N192 : STD_LOGIC; 
  signal UUT_counter_4_BXINV_4778 : STD_LOGIC; 
  signal N191 : STD_LOGIC; 
  signal UUT_counter_4_CLKINV_4771 : STD_LOGIC; 
  signal UUT_counter_3_DXMUX_4818 : STD_LOGIC; 
  signal UUT_counter_3_F5MUX_4816 : STD_LOGIC; 
  signal N186 : STD_LOGIC; 
  signal UUT_counter_3_BXINV_4809 : STD_LOGIC; 
  signal N185 : STD_LOGIC; 
  signal UUT_counter_3_CLKINV_4801 : STD_LOGIC; 
  signal UUT_counter_2_DXMUX_4849 : STD_LOGIC; 
  signal UUT_counter_2_F5MUX_4847 : STD_LOGIC; 
  signal N194 : STD_LOGIC; 
  signal UUT_counter_2_BXINV_4840 : STD_LOGIC; 
  signal N193 : STD_LOGIC; 
  signal UUT_counter_2_CLKINV_4833 : STD_LOGIC; 
  signal UUT_counter_1_DXMUX_4880 : STD_LOGIC; 
  signal UUT_counter_1_F5MUX_4878 : STD_LOGIC; 
  signal N188 : STD_LOGIC; 
  signal UUT_counter_1_BXINV_4870 : STD_LOGIC; 
  signal N187 : STD_LOGIC; 
  signal UUT_counter_1_CLKINV_4862 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In37_F5MUX_4907 : STD_LOGIC; 
  signal N196 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In37_BXINV_4900 : STD_LOGIC; 
  signal N195 : STD_LOGIC; 
  signal N103_F5MUX_4932 : STD_LOGIC; 
  signal N139 : STD_LOGIC; 
  signal N103_BXINV_4925 : STD_LOGIC; 
  signal N138 : STD_LOGIC; 
  signal N106_F5MUX_4957 : STD_LOGIC; 
  signal N141 : STD_LOGIC; 
  signal N106_BXINV_4950 : STD_LOGIC; 
  signal N140 : STD_LOGIC; 
  signal N33 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux0000231_O_pack_1 : STD_LOGIC; 
  signal UUT_Dir_mux000011_5004 : STD_LOGIC; 
  signal UUT_Dir_mux000011_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000094_5028 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000091_O_pack_1 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_115_5052 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_115_SW0_O_pack_1 : STD_LOGIC; 
  signal N98 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_1129_pack_1 : STD_LOGIC; 
  signal UUT_N50 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_cmp_eq00001_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_pstate_3_DXMUX_5129 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_1178_SW1_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_pstate_3_CLKINV_5114 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_DXMUX_5161 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux0000 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000034_O_pack_1 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_CLKINV_5146 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_CEINV_5145 : STD_LOGIC; 
  signal UUT_N3 : STD_LOGIC; 
  signal UUT_N362_pack_1 : STD_LOGIC; 
  signal UUT_Dir_mux0000121_5211 : STD_LOGIC; 
  signal UUT_Dir_mux0000108_O_pack_1 : STD_LOGIC; 
  signal UUT_N3157_5235 : STD_LOGIC; 
  signal UUT_N3157_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_N3178_5259 : STD_LOGIC; 
  signal UUT_N3106_O_pack_1 : STD_LOGIC; 
  signal UUT_Dir_mux000061 : STD_LOGIC; 
  signal UUT_Dir_mux0000611_SW0_O_pack_1 : STD_LOGIC; 
  signal N51 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux00002_SW0_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_and0000 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq00031_SW1_O_pack_1 : STD_LOGIC; 
  signal UUT_nstate_FFd3_DXMUX_5361 : STD_LOGIC; 
  signal UUT_nstate_FFd3_FXMUX_5360 : STD_LOGIC; 
  signal UUT_nstate_FFd3_In_5358 : STD_LOGIC; 
  signal UUT_nstate_FFd3_In_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_nstate_FFd3_CLKINV_5345 : STD_LOGIC; 
  signal UUT_N31 : STD_LOGIC; 
  signal UUT_shiftReg_or0000_pack_1 : STD_LOGIC; 
  signal UUT_N14 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_10_25_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_N320_5968 : STD_LOGIC; 
  signal UUT_N33_O_pack_1 : STD_LOGIC; 
  signal UUT_N349_5992 : STD_LOGIC; 
  signal UUT_ack_count_and0025_pack_1 : STD_LOGIC; 
  signal UUT_N62 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0010_pack_1 : STD_LOGIC; 
  signal UUT_N392_6040 : STD_LOGIC; 
  signal UUT_N392_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_or000017_6064 : STD_LOGIC; 
  signal UUT_shiftReg_or000012_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_110_6088 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_131_O_pack_1 : STD_LOGIC; 
  signal UUT_N13 : STD_LOGIC; 
  signal UUT_N45_pack_1 : STD_LOGIC; 
  signal UUT_N0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_119_SW1_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_216_6160 : STD_LOGIC; 
  signal UUT_N33_pack_1 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_DXMUX_6191 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux0000 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux00009_O_pack_1 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_CLKINV_6176 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_CEINV_6175 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux0000133_6217 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux0000113_O_pack_1 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000104_6241 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000053_O_pack_1 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not0001 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not0001125_O_pack_1 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000176_6289 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000163_O_pack_1 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not0001168_6313 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not0001168_SW0_O_pack_1 : STD_LOGIC; 
  signal N25 : STD_LOGIC; 
  signal UUT_delay_count_or0000_pack_1 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0000_6361 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0000_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0001_6385 : STD_LOGIC; 
  signal UUT_N60_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_6_DXMUX_6416 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_6_18 : STD_LOGIC; 
  signal UUT_N12_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_6_SRINV_6401 : STD_LOGIC; 
  signal UUT_shiftReg_6_CLKINV_6400 : STD_LOGIC; 
  signal UUT_shiftReg_1_DXMUX_6449 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_1_1_6446 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_1_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_1_SRINV_6433 : STD_LOGIC; 
  signal UUT_shiftReg_1_CLKINV_6432 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_8_6475 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_5_O_pack_1 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_28_5410 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_18_O_pack_1 : STD_LOGIC; 
  signal UUT_N211 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_cmp_eq0000_pack_1 : STD_LOGIC; 
  signal UUT_N331 : STD_LOGIC; 
  signal UUT_shiftReg_or00002_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000026_5482 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000026_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not000141_5506 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not000111_O_pack_1 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000047_5530 : STD_LOGIC; 
  signal UUT_N57_pack_1 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000066_5554 : STD_LOGIC; 
  signal UUT_N27_pack_1 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000097_5578 : STD_LOGIC; 
  signal UUT_N41_pack_1 : STD_LOGIC; 
  signal N153 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0011_pack_1 : STD_LOGIC; 
  signal N114 : STD_LOGIC; 
  signal UUT_N64_pack_1 : STD_LOGIC; 
  signal UUT_Dir_DXMUX_5657 : STD_LOGIC; 
  signal UUT_Dir_mux0000224 : STD_LOGIC; 
  signal UUT_Dir_mux0000194_SW1_O_pack_1 : STD_LOGIC; 
  signal UUT_Dir_SRINV_5642 : STD_LOGIC; 
  signal UUT_Dir_CLKINV_5641 : STD_LOGIC; 
  signal N35 : STD_LOGIC; 
  signal UUT_N511_pack_1 : STD_LOGIC; 
  signal N56 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_1175_pack_1 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_10_23_5731 : STD_LOGIC; 
  signal UUT_ack_count_cmp_eq0003_pack_1 : STD_LOGIC; 
  signal N96 : STD_LOGIC; 
  signal N49_pack_1 : STD_LOGIC; 
  signal UUT_writeCount_8_DXMUX_5784 : STD_LOGIC; 
  signal UUT_N35_pack_1 : STD_LOGIC; 
  signal UUT_writeCount_8_CLKINV_5768 : STD_LOGIC; 
  signal UUT_writeCount_9_DXMUX_5814 : STD_LOGIC; 
  signal UUT_N11_pack_1 : STD_LOGIC; 
  signal UUT_writeCount_9_CLKINV_5799 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux000061_5839 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux000061_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux000055_5863 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0008_pack_1 : STD_LOGIC; 
  signal UUT_ack_count_0_DXMUX_5894 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_60 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_43_O_pack_1 : STD_LOGIC; 
  signal UUT_ack_count_0_SRINV_5879 : STD_LOGIC; 
  signal UUT_ack_count_0_CLKINV_5878 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0002 : STD_LOGIC; 
  signal UUT_Dir_mux00012_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_4_3_7040 : STD_LOGIC; 
  signal UUT_shiftReg_2_DYMUX_7030 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_2_11 : STD_LOGIC; 
  signal UUT_shiftReg_2_SRINV_7022 : STD_LOGIC; 
  signal UUT_shiftReg_2_CLKINV_7021 : STD_LOGIC; 
  signal UUT_shiftReg_3_DYMUX_7059 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_3_23 : STD_LOGIC; 
  signal UUT_shiftReg_3_SRINV_7051 : STD_LOGIC; 
  signal UUT_shiftReg_3_CLKINV_7050 : STD_LOGIC; 
  signal UUT_shiftReg_4_DYMUX_7080 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_4_11 : STD_LOGIC; 
  signal UUT_shiftReg_4_SRINV_7072 : STD_LOGIC; 
  signal UUT_shiftReg_4_CLKINV_7071 : STD_LOGIC; 
  signal UUT_writeCount_30_DXMUX_7115 : STD_LOGIC; 
  signal UUT_writeCount_30_DYMUX_7104 : STD_LOGIC; 
  signal UUT_writeCount_30_CLKINV_7096 : STD_LOGIC; 
  signal UUT_writeCount_3_DXMUX_7149 : STD_LOGIC; 
  signal UUT_writeCount_3_DYMUX_7138 : STD_LOGIC; 
  signal UUT_writeCount_3_CLKINV_7130 : STD_LOGIC; 
  signal UUT_writeCount_5_DXMUX_7183 : STD_LOGIC; 
  signal UUT_writeCount_5_DYMUX_7172 : STD_LOGIC; 
  signal UUT_writeCount_5_CLKINV_7164 : STD_LOGIC; 
  signal UUT_writeCount_7_DXMUX_7217 : STD_LOGIC; 
  signal UUT_writeCount_7_DYMUX_7206 : STD_LOGIC; 
  signal UUT_writeCount_7_CLKINV_7198 : STD_LOGIC; 
  signal UUT_ClkFallingEdge_not0001 : STD_LOGIC; 
  signal UUT_prevClk_DYMUX_7239 : STD_LOGIC; 
  signal UUT_prevClk_mux0000 : STD_LOGIC; 
  signal UUT_prevClk_CLKINV_7230 : STD_LOGIC; 
  signal UUT_ClkRisingEdge_DYMUX_7267 : STD_LOGIC; 
  signal UUT_ClkRisingEdge_and00001 : STD_LOGIC; 
  signal UUT_ClkRisingEdge_SRINV_7257 : STD_LOGIC; 
  signal UUT_ClkRisingEdge_CLKINV_7256 : STD_LOGIC; 
  signal N13 : STD_LOGIC; 
  signal UUT_pstate_2_DYMUX_7291 : STD_LOGIC; 
  signal UUT_pstate_2_CLKINV_7283 : STD_LOGIC; 
  signal UUT_delay_count_0_DYMUX_7318 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_25 : STD_LOGIC; 
  signal UUT_delay_count_0_SRINV_7308 : STD_LOGIC; 
  signal UUT_delay_count_0_CLKINV_7307 : STD_LOGIC; 
  signal UUT_shiftReg_or000032_7350 : STD_LOGIC; 
  signal UUT_delay_count_1_DYMUX_7341 : STD_LOGIC; 
  signal UUT_delay_count_1_CLKINV_7333 : STD_LOGIC; 
  signal UUT_delay_count_3_DXMUX_7383 : STD_LOGIC; 
  signal UUT_delay_count_3_DYMUX_7372 : STD_LOGIC; 
  signal UUT_delay_count_3_CLKINV_7364 : STD_LOGIC; 
  signal UUT_delay_count_5_DXMUX_7417 : STD_LOGIC; 
  signal UUT_delay_count_5_DYMUX_7406 : STD_LOGIC; 
  signal UUT_delay_count_5_CLKINV_7398 : STD_LOGIC; 
  signal UUT_delay_count_7_DXMUX_7451 : STD_LOGIC; 
  signal UUT_delay_count_7_DYMUX_7440 : STD_LOGIC; 
  signal UUT_delay_count_7_CLKINV_7432 : STD_LOGIC; 
  signal UUT_delay_count_9_DXMUX_7485 : STD_LOGIC; 
  signal UUT_delay_count_9_DYMUX_7474 : STD_LOGIC; 
  signal UUT_delay_count_9_CLKINV_7466 : STD_LOGIC; 
  signal UUT_ack_count_11_DXMUX_7519 : STD_LOGIC; 
  signal UUT_ack_count_11_DYMUX_7508 : STD_LOGIC; 
  signal UUT_ack_count_11_CLKINV_7500 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_3_8_6499 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_3_5_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_5_DXMUX_6530 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_5_1_6527 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_5_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_5_SRINV_6514 : STD_LOGIC; 
  signal UUT_shiftReg_5_CLKINV_6513 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_6_5_6556 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_6_3_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_7_DXMUX_6587 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_7_1_6584 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_119_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_7_SRINV_6572 : STD_LOGIC; 
  signal UUT_shiftReg_7_CLKINV_6571 : STD_LOGIC; 
  signal UUT_N38 : STD_LOGIC; 
  signal N53_pack_1 : STD_LOGIC; 
  signal UUT_N112 : STD_LOGIC; 
  signal UUT_counter_mux0000_4_1_SW0_O_pack_1 : STD_LOGIC; 
  signal N128 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000027_SW0_SW0_O_pack_1 : STD_LOGIC; 
  signal N86 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_111_SW1_O_pack_1 : STD_LOGIC; 
  signal UUT_N15 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_11_1_SW1_O_pack_1 : STD_LOGIC; 
  signal UUT_out_i2cclk_DXMUX_6740 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000263 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000204_O_pack_1 : STD_LOGIC; 
  signal UUT_out_i2cclk_SRINV_6725 : STD_LOGIC; 
  signal UUT_out_i2cclk_CLKINV_6724 : STD_LOGIC; 
  signal UUT_delay_count_and0000 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq00031_SW2_O_pack_1 : STD_LOGIC; 
  signal UUT_nstate_FFd4_DXMUX_6798 : STD_LOGIC; 
  signal UUT_nstate_FFd4_FXMUX_6797 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In79 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In77_O_pack_1 : STD_LOGIC; 
  signal UUT_nstate_FFd4_SRINV_6781 : STD_LOGIC; 
  signal UUT_nstate_FFd4_CLKINV_6780 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_18_6824 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_18_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_117_6848 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_181_O_pack_1 : STD_LOGIC; 
  signal UUT_N4 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_146_O_pack_1 : STD_LOGIC; 
  signal UUT_delay_count_11_DXMUX_6905 : STD_LOGIC; 
  signal UUT_delay_count_11_DYMUX_6894 : STD_LOGIC; 
  signal UUT_delay_count_11_CLKINV_6886 : STD_LOGIC; 
  signal UUT_delay_count_13_DXMUX_6939 : STD_LOGIC; 
  signal UUT_delay_count_13_DYMUX_6928 : STD_LOGIC; 
  signal UUT_delay_count_13_CLKINV_6920 : STD_LOGIC; 
  signal UUT_delay_count_15_DXMUX_6973 : STD_LOGIC; 
  signal UUT_delay_count_15_DYMUX_6962 : STD_LOGIC; 
  signal UUT_delay_count_15_CLKINV_6954 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000054_7007 : STD_LOGIC; 
  signal UUT_shiftReg_0_DYMUX_6997 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_231 : STD_LOGIC; 
  signal UUT_shiftReg_0_SRINV_6989 : STD_LOGIC; 
  signal UUT_shiftReg_0_CLKINV_6988 : STD_LOGIC; 
  signal UUT_Mtrien_in_i2c_mux000041_7550 : STD_LOGIC; 
  signal UUT_ack_count_1_DYMUX_7540 : STD_LOGIC; 
  signal UUT_ack_count_1_CLKINV_7532 : STD_LOGIC; 
  signal UUT_ack_count_3_DXMUX_7583 : STD_LOGIC; 
  signal UUT_ack_count_3_DYMUX_7572 : STD_LOGIC; 
  signal UUT_ack_count_3_CLKINV_7564 : STD_LOGIC; 
  signal UUT_ack_count_5_DXMUX_7617 : STD_LOGIC; 
  signal UUT_ack_count_5_DYMUX_7606 : STD_LOGIC; 
  signal UUT_ack_count_5_CLKINV_7598 : STD_LOGIC; 
  signal UUT_ack_count_7_DXMUX_7651 : STD_LOGIC; 
  signal UUT_ack_count_7_DYMUX_7640 : STD_LOGIC; 
  signal UUT_ack_count_7_CLKINV_7632 : STD_LOGIC; 
  signal UUT_ack_count_9_DXMUX_7685 : STD_LOGIC; 
  signal UUT_ack_count_9_DYMUX_7674 : STD_LOGIC; 
  signal UUT_ack_count_9_CLKINV_7666 : STD_LOGIC; 
  signal UUT_writeCount_11_DXMUX_7719 : STD_LOGIC; 
  signal UUT_writeCount_11_DYMUX_7708 : STD_LOGIC; 
  signal UUT_writeCount_11_CLKINV_7700 : STD_LOGIC; 
  signal UUT_writeCount_13_DXMUX_7753 : STD_LOGIC; 
  signal UUT_writeCount_13_DYMUX_7742 : STD_LOGIC; 
  signal UUT_writeCount_13_CLKINV_7734 : STD_LOGIC; 
  signal UUT_writeCount_21_DXMUX_7787 : STD_LOGIC; 
  signal UUT_writeCount_21_DYMUX_7776 : STD_LOGIC; 
  signal UUT_writeCount_21_CLKINV_7768 : STD_LOGIC; 
  signal UUT_writeCount_15_DXMUX_7821 : STD_LOGIC; 
  signal UUT_writeCount_15_DYMUX_7810 : STD_LOGIC; 
  signal UUT_writeCount_15_CLKINV_7802 : STD_LOGIC; 
  signal UUT_writeCount_23_DXMUX_7855 : STD_LOGIC; 
  signal UUT_writeCount_23_DYMUX_7844 : STD_LOGIC; 
  signal UUT_writeCount_23_CLKINV_7836 : STD_LOGIC; 
  signal UUT_writeCount_17_DXMUX_7889 : STD_LOGIC; 
  signal UUT_writeCount_17_DYMUX_7878 : STD_LOGIC; 
  signal UUT_writeCount_17_CLKINV_7870 : STD_LOGIC; 
  signal UUT_writeCount_25_DXMUX_7923 : STD_LOGIC; 
  signal UUT_writeCount_25_DYMUX_7912 : STD_LOGIC; 
  signal UUT_writeCount_25_CLKINV_7904 : STD_LOGIC; 
  signal UUT_writeCount_19_DXMUX_7957 : STD_LOGIC; 
  signal UUT_writeCount_19_DYMUX_7946 : STD_LOGIC; 
  signal UUT_writeCount_19_CLKINV_7938 : STD_LOGIC; 
  signal UUT_writeCount_27_DXMUX_7991 : STD_LOGIC; 
  signal UUT_writeCount_27_DYMUX_7980 : STD_LOGIC; 
  signal UUT_writeCount_27_CLKINV_7972 : STD_LOGIC; 
  signal UUT_writeCount_29_DXMUX_8025 : STD_LOGIC; 
  signal UUT_writeCount_29_DYMUX_8014 : STD_LOGIC; 
  signal UUT_writeCount_29_CLKINV_8006 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux0000119_8050 : STD_LOGIC; 
  signal UUT_N32 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_25_8074 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000065_8066 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000131_8098 : STD_LOGIC; 
  signal UUT_N65 : STD_LOGIC; 
  signal UUT_in_i2c : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_mux000078_8113 : STD_LOGIC; 
  signal UUT_N327_8146 : STD_LOGIC; 
  signal UUT_Dir_mux000058_8139 : STD_LOGIC; 
  signal UUT_Mtridata_in_i2c_not00012_8170 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux00002_8163 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_2_3_8194 : STD_LOGIC; 
  signal UUT_counter_mux0000_4_11 : STD_LOGIC; 
  signal N116 : STD_LOGIC; 
  signal UUT_N351 : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq00007_8230 : STD_LOGIC; 
  signal UUT_Dir_mux0000169_8254 : STD_LOGIC; 
  signal UUT_Dir_mux0000143_pack_1 : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal UUT_N53 : STD_LOGIC; 
  signal N71 : STD_LOGIC; 
  signal UUT_Dir_mux0000148_8295 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0005 : STD_LOGIC; 
  signal UUT_N69 : STD_LOGIC; 
  signal UUT_counter_0_DXMUX_8357 : STD_LOGIC; 
  signal UUT_counter_mux0000_4_24_8354 : STD_LOGIC; 
  signal N169_pack_1 : STD_LOGIC; 
  signal UUT_counter_0_SRINV_8342 : STD_LOGIC; 
  signal UUT_counter_0_CLKINV_8341 : STD_LOGIC; 
  signal UUT_pstate_mux0000_5_1155_8371 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_122_8395 : STD_LOGIC; 
  signal N58 : STD_LOGIC; 
  signal CLK_sI2C_Clk_DYMUX_8405 : STD_LOGIC; 
  signal CLK_sI2C_Clk_CLKINV_8403 : STD_LOGIC; 
  signal CLK_sI2C_Clk_CEINV_8402 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000118_8431 : STD_LOGIC; 
  signal N159 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000162_8455 : STD_LOGIC; 
  signal N181 : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq0000 : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq000016_pack_1 : STD_LOGIC; 
  signal N146 : STD_LOGIC; 
  signal UUT_ClkEdge_1_DXMUX_8506 : STD_LOGIC; 
  signal UUT_ClkEdge_1_DYMUX_8501 : STD_LOGIC; 
  signal UUT_ClkEdge_1_CLKINV_8499 : STD_LOGIC; 
  signal UUT_Dir_mux000082_8531 : STD_LOGIC; 
  signal N183_pack_1 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0006 : STD_LOGIC; 
  signal N134 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In0_8567 : STD_LOGIC; 
  signal N123 : STD_LOGIC; 
  signal N95 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0012 : STD_LOGIC; 
  signal UUT_N26 : STD_LOGIC; 
  signal N102 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_240_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_114 : STD_LOGIC; 
  signal UUT_nstate_FFd1_1_DYMUX_8661 : STD_LOGIC; 
  signal UUT_nstate_FFd1_1_SRINV_8659 : STD_LOGIC; 
  signal UUT_nstate_FFd1_1_CLKINV_8658 : STD_LOGIC; 
  signal UUT_nstate_FFd2_1_DYMUX_8673 : STD_LOGIC; 
  signal UUT_nstate_FFd2_1_SRINV_8671 : STD_LOGIC; 
  signal UUT_nstate_FFd2_1_CLKINV_8670 : STD_LOGIC; 
  signal UUT_nstate_FFd3_1_DYMUX_8683 : STD_LOGIC; 
  signal UUT_nstate_FFd3_1_CLKINV_8681 : STD_LOGIC; 
  signal UUT_nstate_FFd4_1_DYMUX_8694 : STD_LOGIC; 
  signal UUT_nstate_FFd4_1_SRINV_8692 : STD_LOGIC; 
  signal UUT_nstate_FFd4_1_CLKINV_8691 : STD_LOGIC; 
  signal N39 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000216_8713 : STD_LOGIC; 
  signal N42 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_0_8737 : STD_LOGIC; 
  signal UUT_ClkFallingEdge_DYMUX_8754 : STD_LOGIC; 
  signal UUT_ClkFallingEdge_SRINV_8752 : STD_LOGIC; 
  signal UUT_ClkFallingEdge_CLKINV_8751 : STD_LOGIC; 
  signal N126 : STD_LOGIC; 
  signal N119 : STD_LOGIC; 
  signal N157 : STD_LOGIC; 
  signal N43 : STD_LOGIC; 
  signal N69 : STD_LOGIC; 
  signal N78 : STD_LOGIC; 
  signal N77 : STD_LOGIC; 
  signal UUT_N67 : STD_LOGIC; 
  signal N105 : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal UUT_writeCount : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal UUT_writeCount_share0000 : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal UUT_Madd_writeCount_share0000_cy : STD_LOGIC_VECTOR ( 28 downto 0 ); 
  signal UUT_delay_count : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal UUT_ack_count : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal UUT_ack_count_share0000 : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal UUT_delay_count_share0000 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal CLK_clk_div : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal UUT_pstate : STD_LOGIC_VECTOR ( 3 downto 2 ); 
  signal UUT_counter : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal UUT_shiftReg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal UUT_ClkEdge : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal UUT_shiftReg_cmp_eq0001_wg_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal UUT_shiftReg_cmp_eq0001_wg_cy : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal UUT_Madd_delay_count_share0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal UUT_Madd_ack_count_share0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal UUT_Madd_writeCount_share0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal CLK_Mcount_clk_div_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal UUT_pstate_mux0000 : STD_LOGIC_VECTOR ( 6 downto 5 ); 
  signal UUT_writeCount_mux0000 : STD_LOGIC_VECTOR ( 30 downto 1 ); 
  signal UUT_delay_count_mux0000 : STD_LOGIC_VECTOR ( 15 downto 1 ); 
  signal UUT_ack_count_mux0000 : STD_LOGIC_VECTOR ( 11 downto 1 ); 
  signal UUT_Madd_counter_addsub0000_cy : STD_LOGIC_VECTOR ( 2 downto 2 ); 
begin
  UUT_ack_count_share0000_8_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y63"
    )
    port map (
      O => UUT_ack_count_share0000_8_LOGIC_ZERO_3543
    );
  UUT_ack_count_share0000_8_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y63",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_8_XORF_3563,
      O => UUT_ack_count_share0000(8)
    );
  UUT_ack_count_share0000_8_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y63"
    )
    port map (
      I0 => UUT_ack_count_share0000_8_CYINIT_3562,
      I1 => UUT_ack_count_share0000_8_F,
      O => UUT_ack_count_share0000_8_XORF_3563
    );
  UUT_ack_count_share0000_8_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y63"
    )
    port map (
      IA => UUT_ack_count_share0000_8_LOGIC_ZERO_3543,
      IB => UUT_ack_count_share0000_8_CYINIT_3562,
      SEL => UUT_ack_count_share0000_8_CYSELF_3549,
      O => UUT_Madd_ack_count_share0000_cy_8_Q
    );
  UUT_ack_count_share0000_8_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y63"
    )
    port map (
      IA => UUT_ack_count_share0000_8_LOGIC_ZERO_3543,
      IB => UUT_ack_count_share0000_8_LOGIC_ZERO_3543,
      SEL => UUT_ack_count_share0000_8_CYSELF_3549,
      O => UUT_ack_count_share0000_8_CYMUXF2_3544
    );
  UUT_ack_count_share0000_8_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y63",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_7_Q,
      O => UUT_ack_count_share0000_8_CYINIT_3562
    );
  UUT_ack_count_share0000_8_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y63",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_8_F,
      O => UUT_ack_count_share0000_8_CYSELF_3549
    );
  UUT_ack_count_share0000_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y63",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_8_XORG_3551,
      O => UUT_ack_count_share0000(9)
    );
  UUT_ack_count_share0000_8_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y63"
    )
    port map (
      I0 => UUT_Madd_ack_count_share0000_cy_8_Q,
      I1 => UUT_ack_count_share0000_8_G,
      O => UUT_ack_count_share0000_8_XORG_3551
    );
  UUT_ack_count_share0000_8_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y63",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_7_Q,
      O => UUT_ack_count_share0000_8_FASTCARRY_3546
    );
  UUT_ack_count_share0000_8_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y63"
    )
    port map (
      I0 => UUT_ack_count_share0000_8_CYSELG_3534,
      I1 => UUT_ack_count_share0000_8_CYSELF_3549,
      O => UUT_ack_count_share0000_8_CYAND_3547
    );
  UUT_ack_count_share0000_8_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y63"
    )
    port map (
      IA => UUT_ack_count_share0000_8_CYMUXG2_3545,
      IB => UUT_ack_count_share0000_8_FASTCARRY_3546,
      SEL => UUT_ack_count_share0000_8_CYAND_3547,
      O => UUT_ack_count_share0000_8_CYMUXFAST_3548
    );
  UUT_ack_count_share0000_8_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y63"
    )
    port map (
      IA => UUT_ack_count_share0000_8_LOGIC_ZERO_3543,
      IB => UUT_ack_count_share0000_8_CYMUXF2_3544,
      SEL => UUT_ack_count_share0000_8_CYSELG_3534,
      O => UUT_ack_count_share0000_8_CYMUXG2_3545
    );
  UUT_ack_count_share0000_8_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y63",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_8_G,
      O => UUT_ack_count_share0000_8_CYSELG_3534
    );
  UUT_ack_count_share0000_10_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y64"
    )
    port map (
      O => UUT_ack_count_share0000_10_LOGIC_ZERO_3593
    );
  UUT_ack_count_share0000_10_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y64",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_10_XORF_3594,
      O => UUT_ack_count_share0000(10)
    );
  UUT_ack_count_share0000_10_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y64"
    )
    port map (
      I0 => UUT_ack_count_share0000_10_CYINIT_3592,
      I1 => UUT_ack_count_share0000_10_F,
      O => UUT_ack_count_share0000_10_XORF_3594
    );
  UUT_ack_count_share0000_10_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y64"
    )
    port map (
      IA => UUT_ack_count_share0000_10_LOGIC_ZERO_3593,
      IB => UUT_ack_count_share0000_10_CYINIT_3592,
      SEL => UUT_ack_count_share0000_10_CYSELF_3583,
      O => UUT_Madd_ack_count_share0000_cy_10_Q
    );
  UUT_ack_count_share0000_10_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y64",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_8_CYMUXFAST_3548,
      O => UUT_ack_count_share0000_10_CYINIT_3592
    );
  UUT_ack_count_share0000_10_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y64",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_10_F,
      O => UUT_ack_count_share0000_10_CYSELF_3583
    );
  UUT_ack_count_share0000_10_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y64",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_10_XORG_3580,
      O => UUT_ack_count_share0000(11)
    );
  UUT_ack_count_share0000_10_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y64"
    )
    port map (
      I0 => UUT_Madd_ack_count_share0000_cy_10_Q,
      I1 => UUT_ack_count_11_rt_3577,
      O => UUT_ack_count_share0000_10_XORG_3580
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X29Y52"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ONE_3613
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X29Y52"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ZERO_3625
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X29Y52"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ZERO_3625,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYINIT_3624,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELF_3618,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_0_1
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X29Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYINIT_3624
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X29Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut_0_1_3617,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELF_3618
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X29Y52"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ONE_3613,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_0_1,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELG_3605,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYMUXG_3615
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X29Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut_1_1_3604,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELG_3605
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X29Y53"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3643
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X29Y53"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3643,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3643,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELF_3649,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXF2_3644
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X29Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut_2_1_3650,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELF_3649
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXFAST_3648,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X29Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYMUXG_3615,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_FASTCARRY_3646
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X29Y53"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELG_3635,
      I1 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELF_3649,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYAND_3647
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X29Y53"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXG2_3645,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_FASTCARRY_3646,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYAND_3647,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXFAST_3648
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X29Y53"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3643,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXF2_3644,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELG_3635,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXG2_3645
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X29Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut_3_1_3634,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELG_3635
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X35Y5"
    )
    port map (
      O => UUT_shiftReg_cmp_eq0001_wg_cy_1_LOGIC_ZERO_3672
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X35Y5"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_1_LOGIC_ZERO_3672,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYINIT_3684,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELF_3677,
      O => UUT_shiftReg_cmp_eq0001_wg_cy(0)
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X35Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYINIT_3684
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(0),
      O => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELF_3677
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X35Y5"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_1_LOGIC_ZERO_3672,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy(0),
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELG_3666,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYMUXG_3674
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(1),
      O => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELG_3666
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X35Y6"
    )
    port map (
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_LOGIC_ZERO_3702
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y6"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_3_LOGIC_ZERO_3702,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_3_LOGIC_ZERO_3702,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELF_3708,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXF2_3703
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(2),
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELF_3708
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X35Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYMUXG_3674,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_FASTCARRY_3705
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X35Y6"
    )
    port map (
      I0 => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELG_3696,
      I1 => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELF_3708,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYAND_3706
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X35Y6"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXG2_3704,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_3_FASTCARRY_3705,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYAND_3706,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXFAST_3707
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y6"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_3_LOGIC_ZERO_3702,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXF2_3703,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELG_3696,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXG2_3704
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(3),
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELG_3696
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X35Y7"
    )
    port map (
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_LOGIC_ZERO_3732
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y7"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_5_LOGIC_ZERO_3732,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_5_LOGIC_ZERO_3732,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELF_3738,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXF2_3733
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(4),
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELF_3738
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X35Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXFAST_3707,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_FASTCARRY_3735
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X35Y7"
    )
    port map (
      I0 => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELG_3726,
      I1 => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELF_3738,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYAND_3736
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X35Y7"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXG2_3734,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_5_FASTCARRY_3735,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYAND_3736,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXFAST_3737
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y7"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_5_LOGIC_ZERO_3732,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXF2_3733,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELG_3726,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXG2_3734
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(5),
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELG_3726
    );
  UUT_shiftReg_cmp_eq0001_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X35Y8"
    )
    port map (
      O => UUT_shiftReg_cmp_eq0001_LOGIC_ZERO_3762
    );
  UUT_shiftReg_cmp_eq0001_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y8"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_LOGIC_ZERO_3762,
      IB => UUT_shiftReg_cmp_eq0001_LOGIC_ZERO_3762,
      SEL => UUT_shiftReg_cmp_eq0001_CYSELF_3768,
      O => UUT_shiftReg_cmp_eq0001_CYMUXF2_3763
    );
  UUT_shiftReg_cmp_eq0001_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(6),
      O => UUT_shiftReg_cmp_eq0001_CYSELF_3768
    );
  UUT_shiftReg_cmp_eq0001_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X35Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_CYMUXFAST_3767,
      O => UUT_shiftReg_cmp_eq0001
    );
  UUT_shiftReg_cmp_eq0001_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X35Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXFAST_3737,
      O => UUT_shiftReg_cmp_eq0001_FASTCARRY_3765
    );
  UUT_shiftReg_cmp_eq0001_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X35Y8"
    )
    port map (
      I0 => UUT_shiftReg_cmp_eq0001_CYSELG_3756,
      I1 => UUT_shiftReg_cmp_eq0001_CYSELF_3768,
      O => UUT_shiftReg_cmp_eq0001_CYAND_3766
    );
  UUT_shiftReg_cmp_eq0001_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X35Y8"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_CYMUXG2_3764,
      IB => UUT_shiftReg_cmp_eq0001_FASTCARRY_3765,
      SEL => UUT_shiftReg_cmp_eq0001_CYAND_3766,
      O => UUT_shiftReg_cmp_eq0001_CYMUXFAST_3767
    );
  UUT_shiftReg_cmp_eq0001_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y8"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_LOGIC_ZERO_3762,
      IB => UUT_shiftReg_cmp_eq0001_CYMUXF2_3763,
      SEL => UUT_shiftReg_cmp_eq0001_CYSELG_3756,
      O => UUT_shiftReg_cmp_eq0001_CYMUXG2_3764
    );
  UUT_shiftReg_cmp_eq0001_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(7),
      O => UUT_shiftReg_cmp_eq0001_CYSELG_3756
    );
  UUT_delay_count_share0000_0_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      O => UUT_delay_count_share0000_0_LOGIC_ZERO_3791
    );
  UUT_delay_count_share0000_0_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      O => UUT_delay_count_share0000_0_LOGIC_ONE_3808
    );
  UUT_delay_count_share0000_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_0_XORF_3809,
      O => UUT_delay_count_share0000(0)
    );
  UUT_delay_count_share0000_0_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      I0 => UUT_delay_count_share0000_0_CYINIT_3807,
      I1 => UUT_Madd_delay_count_share0000_lut(0),
      O => UUT_delay_count_share0000_0_XORF_3809
    );
  UUT_delay_count_share0000_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      IA => UUT_delay_count_share0000_0_LOGIC_ONE_3808,
      IB => UUT_delay_count_share0000_0_CYINIT_3807,
      SEL => UUT_delay_count_share0000_0_CYSELF_3798,
      O => UUT_Madd_delay_count_share0000_cy_0_Q
    );
  UUT_delay_count_share0000_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => UUT_delay_count_share0000_0_CYINIT_3807
    );
  UUT_delay_count_share0000_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_lut(0),
      O => UUT_delay_count_share0000_0_CYSELF_3798
    );
  UUT_delay_count_share0000_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_0_XORG_3794,
      O => UUT_delay_count_share0000(1)
    );
  UUT_delay_count_share0000_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_0_Q,
      I1 => UUT_delay_count_share0000_0_G,
      O => UUT_delay_count_share0000_0_XORG_3794
    );
  UUT_delay_count_share0000_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_0_CYMUXG_3793,
      O => UUT_Madd_delay_count_share0000_cy_1_Q
    );
  UUT_delay_count_share0000_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X21Y20"
    )
    port map (
      IA => UUT_delay_count_share0000_0_LOGIC_ZERO_3791,
      IB => UUT_Madd_delay_count_share0000_cy_0_Q,
      SEL => UUT_delay_count_share0000_0_CYSELG_3782,
      O => UUT_delay_count_share0000_0_CYMUXG_3793
    );
  UUT_delay_count_share0000_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_0_G,
      O => UUT_delay_count_share0000_0_CYSELG_3782
    );
  UUT_delay_count_share0000_2_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      O => UUT_delay_count_share0000_2_LOGIC_ZERO_3827
    );
  UUT_delay_count_share0000_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_2_XORF_3847,
      O => UUT_delay_count_share0000(2)
    );
  UUT_delay_count_share0000_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      I0 => UUT_delay_count_share0000_2_CYINIT_3846,
      I1 => UUT_delay_count_share0000_2_F,
      O => UUT_delay_count_share0000_2_XORF_3847
    );
  UUT_delay_count_share0000_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      IA => UUT_delay_count_share0000_2_LOGIC_ZERO_3827,
      IB => UUT_delay_count_share0000_2_CYINIT_3846,
      SEL => UUT_delay_count_share0000_2_CYSELF_3833,
      O => UUT_Madd_delay_count_share0000_cy_2_Q
    );
  UUT_delay_count_share0000_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      IA => UUT_delay_count_share0000_2_LOGIC_ZERO_3827,
      IB => UUT_delay_count_share0000_2_LOGIC_ZERO_3827,
      SEL => UUT_delay_count_share0000_2_CYSELF_3833,
      O => UUT_delay_count_share0000_2_CYMUXF2_3828
    );
  UUT_delay_count_share0000_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_1_Q,
      O => UUT_delay_count_share0000_2_CYINIT_3846
    );
  UUT_delay_count_share0000_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_2_F,
      O => UUT_delay_count_share0000_2_CYSELF_3833
    );
  UUT_delay_count_share0000_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_2_XORG_3835,
      O => UUT_delay_count_share0000(3)
    );
  UUT_delay_count_share0000_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_2_Q,
      I1 => UUT_delay_count_share0000_2_G,
      O => UUT_delay_count_share0000_2_XORG_3835
    );
  UUT_delay_count_share0000_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_2_CYMUXFAST_3832,
      O => UUT_Madd_delay_count_share0000_cy_3_Q
    );
  UUT_delay_count_share0000_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_1_Q,
      O => UUT_delay_count_share0000_2_FASTCARRY_3830
    );
  UUT_delay_count_share0000_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      I0 => UUT_delay_count_share0000_2_CYSELG_3818,
      I1 => UUT_delay_count_share0000_2_CYSELF_3833,
      O => UUT_delay_count_share0000_2_CYAND_3831
    );
  UUT_delay_count_share0000_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      IA => UUT_delay_count_share0000_2_CYMUXG2_3829,
      IB => UUT_delay_count_share0000_2_FASTCARRY_3830,
      SEL => UUT_delay_count_share0000_2_CYAND_3831,
      O => UUT_delay_count_share0000_2_CYMUXFAST_3832
    );
  UUT_delay_count_share0000_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y21"
    )
    port map (
      IA => UUT_delay_count_share0000_2_LOGIC_ZERO_3827,
      IB => UUT_delay_count_share0000_2_CYMUXF2_3828,
      SEL => UUT_delay_count_share0000_2_CYSELG_3818,
      O => UUT_delay_count_share0000_2_CYMUXG2_3829
    );
  UUT_delay_count_share0000_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_2_G,
      O => UUT_delay_count_share0000_2_CYSELG_3818
    );
  UUT_writeCount_share0000_28_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y14"
    )
    port map (
      O => UUT_writeCount_share0000_28_LOGIC_ZERO_3233
    );
  UUT_writeCount_share0000_28_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_28_XORF_3253,
      O => UUT_writeCount_share0000(28)
    );
  UUT_writeCount_share0000_28_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y14"
    )
    port map (
      I0 => UUT_writeCount_share0000_28_CYINIT_3252,
      I1 => UUT_writeCount_share0000_28_F,
      O => UUT_writeCount_share0000_28_XORF_3253
    );
  UUT_writeCount_share0000_28_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y14"
    )
    port map (
      IA => UUT_writeCount_share0000_28_LOGIC_ZERO_3233,
      IB => UUT_writeCount_share0000_28_CYINIT_3252,
      SEL => UUT_writeCount_share0000_28_CYSELF_3239,
      O => UUT_Madd_writeCount_share0000_cy(28)
    );
  UUT_writeCount_share0000_28_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y14"
    )
    port map (
      IA => UUT_writeCount_share0000_28_LOGIC_ZERO_3233,
      IB => UUT_writeCount_share0000_28_LOGIC_ZERO_3233,
      SEL => UUT_writeCount_share0000_28_CYSELF_3239,
      O => UUT_writeCount_share0000_28_CYMUXF2_3234
    );
  UUT_writeCount_share0000_28_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(27),
      O => UUT_writeCount_share0000_28_CYINIT_3252
    );
  UUT_writeCount_share0000_28_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_28_F,
      O => UUT_writeCount_share0000_28_CYSELF_3239
    );
  UUT_writeCount_share0000_28_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_28_XORG_3241,
      O => UUT_writeCount_share0000(29)
    );
  UUT_writeCount_share0000_28_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y14"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(28),
      I1 => UUT_writeCount_share0000_28_G,
      O => UUT_writeCount_share0000_28_XORG_3241
    );
  UUT_writeCount_share0000_28_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(27),
      O => UUT_writeCount_share0000_28_FASTCARRY_3236
    );
  UUT_writeCount_share0000_28_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y14"
    )
    port map (
      I0 => UUT_writeCount_share0000_28_CYSELG_3224,
      I1 => UUT_writeCount_share0000_28_CYSELF_3239,
      O => UUT_writeCount_share0000_28_CYAND_3237
    );
  UUT_writeCount_share0000_28_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y14"
    )
    port map (
      IA => UUT_writeCount_share0000_28_CYMUXG2_3235,
      IB => UUT_writeCount_share0000_28_FASTCARRY_3236,
      SEL => UUT_writeCount_share0000_28_CYAND_3237,
      O => UUT_writeCount_share0000_28_CYMUXFAST_3238
    );
  UUT_writeCount_share0000_28_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y14"
    )
    port map (
      IA => UUT_writeCount_share0000_28_LOGIC_ZERO_3233,
      IB => UUT_writeCount_share0000_28_CYMUXF2_3234,
      SEL => UUT_writeCount_share0000_28_CYSELG_3224,
      O => UUT_writeCount_share0000_28_CYMUXG2_3235
    );
  UUT_writeCount_share0000_28_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_28_G,
      O => UUT_writeCount_share0000_28_CYSELG_3224
    );
  UUT_writeCount_share0000_30_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_30_XORF_3268,
      O => UUT_writeCount_share0000(30)
    );
  UUT_writeCount_share0000_30_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y15"
    )
    port map (
      I0 => UUT_writeCount_share0000_30_CYINIT_3267,
      I1 => UUT_writeCount_30_rt_3265,
      O => UUT_writeCount_share0000_30_XORF_3268
    );
  UUT_writeCount_share0000_30_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_28_CYMUXFAST_3238,
      O => UUT_writeCount_share0000_30_CYINIT_3267
    );
  UUT_writeCount_30_rt : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X37Y15"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(30),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_30_rt_3265
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X19Y25"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ONE_3284
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X19Y25"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ZERO_3299
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X19Y25"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ZERO_3299,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYINIT_3298,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELF_3289,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_0_Q
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X19Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYINIT_3298
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X19Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_2_rt_3288,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELF_3289
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X19Y25"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ONE_3284,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_0_Q,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELG_3276,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYMUXG_3286
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X19Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_lut_1_Q_3275,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELG_3276
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X19Y26"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ONE_3315
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X19Y26"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ZERO_3330
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X19Y26"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ZERO_3330,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ZERO_3330,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELF_3321,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXF2_3316
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X19Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_lut_2_Q_3322,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELF_3321
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X19Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYMUXG_3286,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_FASTCARRY_3318
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X19Y26"
    )
    port map (
      I0 => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELG_3306,
      I1 => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELF_3321,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYAND_3319
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X19Y26"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXG2_3317,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_FASTCARRY_3318,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYAND_3319,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXFAST_3320
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X19Y26"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ONE_3315,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXF2_3316,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELG_3306,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXG2_3317
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X19Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_lut_3_Q,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELG_3306
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X19Y27"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ONE_3345
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X19Y27"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ZERO_3361
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X19Y27"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ZERO_3361,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ZERO_3361,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELF_3351,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXF2_3346
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X19Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_8_rt_3352,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELF_3351
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X19Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXFAST_3320,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_FASTCARRY_3348
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X19Y27"
    )
    port map (
      I0 => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELG_3339,
      I1 => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELF_3351,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYAND_3349
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X19Y27"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXG2_3347,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_FASTCARRY_3348,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYAND_3349,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXFAST_3350
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X19Y27"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ONE_3345,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXF2_3346,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELG_3339,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXG2_3347
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X19Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_lut_5_Q_3338,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELG_3339
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_6_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X19Y28"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_LOGIC_ONE_3376
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X19Y28"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_LOGIC_ONE_3376,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYINIT_3375,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYSELF_3368,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_Q
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X19Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXFAST_3350,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYINIT_3375
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X19Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_lut_6_Q_3367,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYSELF_3368
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_6_Q : X_LUT4
    generic map(
      INIT => X"0005",
      LOC => "SLICE_X19Y28"
    )
    port map (
      ADR0 => UUT_delay_count(14),
      ADR1 => VCC,
      ADR2 => UUT_delay_count(15),
      ADR3 => UUT_delay_count(13),
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_6_Q_3367
    );
  UUT_ack_count_share0000_0_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y59"
    )
    port map (
      O => UUT_ack_count_share0000_0_LOGIC_ZERO_3393
    );
  UUT_ack_count_share0000_0_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X37Y59"
    )
    port map (
      O => UUT_ack_count_share0000_0_LOGIC_ONE_3410
    );
  UUT_ack_count_share0000_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_0_XORF_3411,
      O => UUT_ack_count_share0000(0)
    );
  UUT_ack_count_share0000_0_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y59"
    )
    port map (
      I0 => UUT_ack_count_share0000_0_CYINIT_3409,
      I1 => UUT_Madd_ack_count_share0000_lut(0),
      O => UUT_ack_count_share0000_0_XORF_3411
    );
  UUT_ack_count_share0000_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y59"
    )
    port map (
      IA => UUT_ack_count_share0000_0_LOGIC_ONE_3410,
      IB => UUT_ack_count_share0000_0_CYINIT_3409,
      SEL => UUT_ack_count_share0000_0_CYSELF_3400,
      O => UUT_Madd_ack_count_share0000_cy_0_Q
    );
  UUT_ack_count_share0000_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => UUT_ack_count_share0000_0_CYINIT_3409
    );
  UUT_ack_count_share0000_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_lut(0),
      O => UUT_ack_count_share0000_0_CYSELF_3400
    );
  UUT_ack_count_share0000_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_0_XORG_3396,
      O => UUT_ack_count_share0000(1)
    );
  UUT_ack_count_share0000_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y59"
    )
    port map (
      I0 => UUT_Madd_ack_count_share0000_cy_0_Q,
      I1 => UUT_ack_count_share0000_0_G,
      O => UUT_ack_count_share0000_0_XORG_3396
    );
  UUT_ack_count_share0000_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_0_CYMUXG_3395,
      O => UUT_Madd_ack_count_share0000_cy_1_Q
    );
  UUT_ack_count_share0000_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X37Y59"
    )
    port map (
      IA => UUT_ack_count_share0000_0_LOGIC_ZERO_3393,
      IB => UUT_Madd_ack_count_share0000_cy_0_Q,
      SEL => UUT_ack_count_share0000_0_CYSELG_3384,
      O => UUT_ack_count_share0000_0_CYMUXG_3395
    );
  UUT_ack_count_share0000_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_0_G,
      O => UUT_ack_count_share0000_0_CYSELG_3384
    );
  UUT_ack_count_share0000_2_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y60"
    )
    port map (
      O => UUT_ack_count_share0000_2_LOGIC_ZERO_3429
    );
  UUT_ack_count_share0000_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_2_XORF_3449,
      O => UUT_ack_count_share0000(2)
    );
  UUT_ack_count_share0000_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y60"
    )
    port map (
      I0 => UUT_ack_count_share0000_2_CYINIT_3448,
      I1 => UUT_ack_count_share0000_2_F,
      O => UUT_ack_count_share0000_2_XORF_3449
    );
  UUT_ack_count_share0000_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y60"
    )
    port map (
      IA => UUT_ack_count_share0000_2_LOGIC_ZERO_3429,
      IB => UUT_ack_count_share0000_2_CYINIT_3448,
      SEL => UUT_ack_count_share0000_2_CYSELF_3435,
      O => UUT_Madd_ack_count_share0000_cy_2_Q
    );
  UUT_ack_count_share0000_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y60"
    )
    port map (
      IA => UUT_ack_count_share0000_2_LOGIC_ZERO_3429,
      IB => UUT_ack_count_share0000_2_LOGIC_ZERO_3429,
      SEL => UUT_ack_count_share0000_2_CYSELF_3435,
      O => UUT_ack_count_share0000_2_CYMUXF2_3430
    );
  UUT_ack_count_share0000_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_1_Q,
      O => UUT_ack_count_share0000_2_CYINIT_3448
    );
  UUT_ack_count_share0000_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_2_F,
      O => UUT_ack_count_share0000_2_CYSELF_3435
    );
  UUT_ack_count_share0000_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_2_XORG_3437,
      O => UUT_ack_count_share0000(3)
    );
  UUT_ack_count_share0000_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y60"
    )
    port map (
      I0 => UUT_Madd_ack_count_share0000_cy_2_Q,
      I1 => UUT_ack_count_share0000_2_G,
      O => UUT_ack_count_share0000_2_XORG_3437
    );
  UUT_ack_count_share0000_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_2_CYMUXFAST_3434,
      O => UUT_Madd_ack_count_share0000_cy_3_Q
    );
  UUT_ack_count_share0000_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_1_Q,
      O => UUT_ack_count_share0000_2_FASTCARRY_3432
    );
  UUT_ack_count_share0000_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y60"
    )
    port map (
      I0 => UUT_ack_count_share0000_2_CYSELG_3420,
      I1 => UUT_ack_count_share0000_2_CYSELF_3435,
      O => UUT_ack_count_share0000_2_CYAND_3433
    );
  UUT_ack_count_share0000_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y60"
    )
    port map (
      IA => UUT_ack_count_share0000_2_CYMUXG2_3431,
      IB => UUT_ack_count_share0000_2_FASTCARRY_3432,
      SEL => UUT_ack_count_share0000_2_CYAND_3433,
      O => UUT_ack_count_share0000_2_CYMUXFAST_3434
    );
  UUT_ack_count_share0000_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y60"
    )
    port map (
      IA => UUT_ack_count_share0000_2_LOGIC_ZERO_3429,
      IB => UUT_ack_count_share0000_2_CYMUXF2_3430,
      SEL => UUT_ack_count_share0000_2_CYSELG_3420,
      O => UUT_ack_count_share0000_2_CYMUXG2_3431
    );
  UUT_ack_count_share0000_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_2_G,
      O => UUT_ack_count_share0000_2_CYSELG_3420
    );
  UUT_ack_count_share0000_4_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y61"
    )
    port map (
      O => UUT_ack_count_share0000_4_LOGIC_ZERO_3467
    );
  UUT_ack_count_share0000_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_4_XORF_3487,
      O => UUT_ack_count_share0000(4)
    );
  UUT_ack_count_share0000_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y61"
    )
    port map (
      I0 => UUT_ack_count_share0000_4_CYINIT_3486,
      I1 => UUT_ack_count_share0000_4_F,
      O => UUT_ack_count_share0000_4_XORF_3487
    );
  UUT_ack_count_share0000_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y61"
    )
    port map (
      IA => UUT_ack_count_share0000_4_LOGIC_ZERO_3467,
      IB => UUT_ack_count_share0000_4_CYINIT_3486,
      SEL => UUT_ack_count_share0000_4_CYSELF_3473,
      O => UUT_Madd_ack_count_share0000_cy_4_Q
    );
  UUT_ack_count_share0000_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y61"
    )
    port map (
      IA => UUT_ack_count_share0000_4_LOGIC_ZERO_3467,
      IB => UUT_ack_count_share0000_4_LOGIC_ZERO_3467,
      SEL => UUT_ack_count_share0000_4_CYSELF_3473,
      O => UUT_ack_count_share0000_4_CYMUXF2_3468
    );
  UUT_ack_count_share0000_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_3_Q,
      O => UUT_ack_count_share0000_4_CYINIT_3486
    );
  UUT_ack_count_share0000_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_4_F,
      O => UUT_ack_count_share0000_4_CYSELF_3473
    );
  UUT_ack_count_share0000_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_4_XORG_3475,
      O => UUT_ack_count_share0000(5)
    );
  UUT_ack_count_share0000_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y61"
    )
    port map (
      I0 => UUT_Madd_ack_count_share0000_cy_4_Q,
      I1 => UUT_ack_count_share0000_4_G,
      O => UUT_ack_count_share0000_4_XORG_3475
    );
  UUT_ack_count_share0000_4_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_4_CYMUXFAST_3472,
      O => UUT_Madd_ack_count_share0000_cy_5_Q
    );
  UUT_ack_count_share0000_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_3_Q,
      O => UUT_ack_count_share0000_4_FASTCARRY_3470
    );
  UUT_ack_count_share0000_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y61"
    )
    port map (
      I0 => UUT_ack_count_share0000_4_CYSELG_3458,
      I1 => UUT_ack_count_share0000_4_CYSELF_3473,
      O => UUT_ack_count_share0000_4_CYAND_3471
    );
  UUT_ack_count_share0000_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y61"
    )
    port map (
      IA => UUT_ack_count_share0000_4_CYMUXG2_3469,
      IB => UUT_ack_count_share0000_4_FASTCARRY_3470,
      SEL => UUT_ack_count_share0000_4_CYAND_3471,
      O => UUT_ack_count_share0000_4_CYMUXFAST_3472
    );
  UUT_ack_count_share0000_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y61"
    )
    port map (
      IA => UUT_ack_count_share0000_4_LOGIC_ZERO_3467,
      IB => UUT_ack_count_share0000_4_CYMUXF2_3468,
      SEL => UUT_ack_count_share0000_4_CYSELG_3458,
      O => UUT_ack_count_share0000_4_CYMUXG2_3469
    );
  UUT_ack_count_share0000_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_4_G,
      O => UUT_ack_count_share0000_4_CYSELG_3458
    );
  UUT_ack_count_share0000_6_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y62"
    )
    port map (
      O => UUT_ack_count_share0000_6_LOGIC_ZERO_3505
    );
  UUT_ack_count_share0000_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y62",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_6_XORF_3525,
      O => UUT_ack_count_share0000(6)
    );
  UUT_ack_count_share0000_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y62"
    )
    port map (
      I0 => UUT_ack_count_share0000_6_CYINIT_3524,
      I1 => UUT_ack_count_share0000_6_F,
      O => UUT_ack_count_share0000_6_XORF_3525
    );
  UUT_ack_count_share0000_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y62"
    )
    port map (
      IA => UUT_ack_count_share0000_6_LOGIC_ZERO_3505,
      IB => UUT_ack_count_share0000_6_CYINIT_3524,
      SEL => UUT_ack_count_share0000_6_CYSELF_3511,
      O => UUT_Madd_ack_count_share0000_cy_6_Q
    );
  UUT_ack_count_share0000_6_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y62"
    )
    port map (
      IA => UUT_ack_count_share0000_6_LOGIC_ZERO_3505,
      IB => UUT_ack_count_share0000_6_LOGIC_ZERO_3505,
      SEL => UUT_ack_count_share0000_6_CYSELF_3511,
      O => UUT_ack_count_share0000_6_CYMUXF2_3506
    );
  UUT_ack_count_share0000_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y62",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_5_Q,
      O => UUT_ack_count_share0000_6_CYINIT_3524
    );
  UUT_ack_count_share0000_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y62",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_6_F,
      O => UUT_ack_count_share0000_6_CYSELF_3511
    );
  UUT_ack_count_share0000_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y62",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_6_XORG_3513,
      O => UUT_ack_count_share0000(7)
    );
  UUT_ack_count_share0000_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y62"
    )
    port map (
      I0 => UUT_Madd_ack_count_share0000_cy_6_Q,
      I1 => UUT_ack_count_share0000_6_G,
      O => UUT_ack_count_share0000_6_XORG_3513
    );
  UUT_ack_count_share0000_6_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y62",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_6_CYMUXFAST_3510,
      O => UUT_Madd_ack_count_share0000_cy_7_Q
    );
  UUT_ack_count_share0000_6_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y62",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_5_Q,
      O => UUT_ack_count_share0000_6_FASTCARRY_3508
    );
  UUT_ack_count_share0000_6_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y62"
    )
    port map (
      I0 => UUT_ack_count_share0000_6_CYSELG_3496,
      I1 => UUT_ack_count_share0000_6_CYSELF_3511,
      O => UUT_ack_count_share0000_6_CYAND_3509
    );
  UUT_ack_count_share0000_6_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y62"
    )
    port map (
      IA => UUT_ack_count_share0000_6_CYMUXG2_3507,
      IB => UUT_ack_count_share0000_6_FASTCARRY_3508,
      SEL => UUT_ack_count_share0000_6_CYAND_3509,
      O => UUT_ack_count_share0000_6_CYMUXFAST_3510
    );
  UUT_ack_count_share0000_6_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y62"
    )
    port map (
      IA => UUT_ack_count_share0000_6_LOGIC_ZERO_3505,
      IB => UUT_ack_count_share0000_6_CYMUXF2_3506,
      SEL => UUT_ack_count_share0000_6_CYSELG_3496,
      O => UUT_ack_count_share0000_6_CYMUXG2_3507
    );
  UUT_ack_count_share0000_6_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y62",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_6_G,
      O => UUT_ack_count_share0000_6_CYSELG_3496
    );
  UUT_writeCount_share0000_10_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y5"
    )
    port map (
      O => UUT_writeCount_share0000_10_LOGIC_ZERO_2891
    );
  UUT_writeCount_share0000_10_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_10_XORF_2911,
      O => UUT_writeCount_share0000(10)
    );
  UUT_writeCount_share0000_10_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y5"
    )
    port map (
      I0 => UUT_writeCount_share0000_10_CYINIT_2910,
      I1 => UUT_writeCount_share0000_10_F,
      O => UUT_writeCount_share0000_10_XORF_2911
    );
  UUT_writeCount_share0000_10_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y5"
    )
    port map (
      IA => UUT_writeCount_share0000_10_LOGIC_ZERO_2891,
      IB => UUT_writeCount_share0000_10_CYINIT_2910,
      SEL => UUT_writeCount_share0000_10_CYSELF_2897,
      O => UUT_Madd_writeCount_share0000_cy(10)
    );
  UUT_writeCount_share0000_10_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y5"
    )
    port map (
      IA => UUT_writeCount_share0000_10_LOGIC_ZERO_2891,
      IB => UUT_writeCount_share0000_10_LOGIC_ZERO_2891,
      SEL => UUT_writeCount_share0000_10_CYSELF_2897,
      O => UUT_writeCount_share0000_10_CYMUXF2_2892
    );
  UUT_writeCount_share0000_10_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(9),
      O => UUT_writeCount_share0000_10_CYINIT_2910
    );
  UUT_writeCount_share0000_10_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_10_F,
      O => UUT_writeCount_share0000_10_CYSELF_2897
    );
  UUT_writeCount_share0000_10_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_10_XORG_2899,
      O => UUT_writeCount_share0000(11)
    );
  UUT_writeCount_share0000_10_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y5"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(10),
      I1 => UUT_writeCount_share0000_10_G,
      O => UUT_writeCount_share0000_10_XORG_2899
    );
  UUT_writeCount_share0000_10_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_10_CYMUXFAST_2896,
      O => UUT_Madd_writeCount_share0000_cy(11)
    );
  UUT_writeCount_share0000_10_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(9),
      O => UUT_writeCount_share0000_10_FASTCARRY_2894
    );
  UUT_writeCount_share0000_10_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y5"
    )
    port map (
      I0 => UUT_writeCount_share0000_10_CYSELG_2882,
      I1 => UUT_writeCount_share0000_10_CYSELF_2897,
      O => UUT_writeCount_share0000_10_CYAND_2895
    );
  UUT_writeCount_share0000_10_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y5"
    )
    port map (
      IA => UUT_writeCount_share0000_10_CYMUXG2_2893,
      IB => UUT_writeCount_share0000_10_FASTCARRY_2894,
      SEL => UUT_writeCount_share0000_10_CYAND_2895,
      O => UUT_writeCount_share0000_10_CYMUXFAST_2896
    );
  UUT_writeCount_share0000_10_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y5"
    )
    port map (
      IA => UUT_writeCount_share0000_10_LOGIC_ZERO_2891,
      IB => UUT_writeCount_share0000_10_CYMUXF2_2892,
      SEL => UUT_writeCount_share0000_10_CYSELG_2882,
      O => UUT_writeCount_share0000_10_CYMUXG2_2893
    );
  UUT_writeCount_share0000_10_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_10_G,
      O => UUT_writeCount_share0000_10_CYSELG_2882
    );
  UUT_writeCount_share0000_12_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y6"
    )
    port map (
      O => UUT_writeCount_share0000_12_LOGIC_ZERO_2929
    );
  UUT_writeCount_share0000_12_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_12_XORF_2949,
      O => UUT_writeCount_share0000(12)
    );
  UUT_writeCount_share0000_12_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y6"
    )
    port map (
      I0 => UUT_writeCount_share0000_12_CYINIT_2948,
      I1 => UUT_writeCount_share0000_12_F,
      O => UUT_writeCount_share0000_12_XORF_2949
    );
  UUT_writeCount_share0000_12_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y6"
    )
    port map (
      IA => UUT_writeCount_share0000_12_LOGIC_ZERO_2929,
      IB => UUT_writeCount_share0000_12_CYINIT_2948,
      SEL => UUT_writeCount_share0000_12_CYSELF_2935,
      O => UUT_Madd_writeCount_share0000_cy(12)
    );
  UUT_writeCount_share0000_12_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y6"
    )
    port map (
      IA => UUT_writeCount_share0000_12_LOGIC_ZERO_2929,
      IB => UUT_writeCount_share0000_12_LOGIC_ZERO_2929,
      SEL => UUT_writeCount_share0000_12_CYSELF_2935,
      O => UUT_writeCount_share0000_12_CYMUXF2_2930
    );
  UUT_writeCount_share0000_12_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(11),
      O => UUT_writeCount_share0000_12_CYINIT_2948
    );
  UUT_writeCount_share0000_12_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_12_F,
      O => UUT_writeCount_share0000_12_CYSELF_2935
    );
  UUT_writeCount_share0000_12_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_12_XORG_2937,
      O => UUT_writeCount_share0000(13)
    );
  UUT_writeCount_share0000_12_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y6"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(12),
      I1 => UUT_writeCount_share0000_12_G,
      O => UUT_writeCount_share0000_12_XORG_2937
    );
  UUT_writeCount_share0000_12_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_12_CYMUXFAST_2934,
      O => UUT_Madd_writeCount_share0000_cy(13)
    );
  UUT_writeCount_share0000_12_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(11),
      O => UUT_writeCount_share0000_12_FASTCARRY_2932
    );
  UUT_writeCount_share0000_12_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y6"
    )
    port map (
      I0 => UUT_writeCount_share0000_12_CYSELG_2920,
      I1 => UUT_writeCount_share0000_12_CYSELF_2935,
      O => UUT_writeCount_share0000_12_CYAND_2933
    );
  UUT_writeCount_share0000_12_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y6"
    )
    port map (
      IA => UUT_writeCount_share0000_12_CYMUXG2_2931,
      IB => UUT_writeCount_share0000_12_FASTCARRY_2932,
      SEL => UUT_writeCount_share0000_12_CYAND_2933,
      O => UUT_writeCount_share0000_12_CYMUXFAST_2934
    );
  UUT_writeCount_share0000_12_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y6"
    )
    port map (
      IA => UUT_writeCount_share0000_12_LOGIC_ZERO_2929,
      IB => UUT_writeCount_share0000_12_CYMUXF2_2930,
      SEL => UUT_writeCount_share0000_12_CYSELG_2920,
      O => UUT_writeCount_share0000_12_CYMUXG2_2931
    );
  UUT_writeCount_share0000_12_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_12_G,
      O => UUT_writeCount_share0000_12_CYSELG_2920
    );
  UUT_writeCount_share0000_14_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y7"
    )
    port map (
      O => UUT_writeCount_share0000_14_LOGIC_ZERO_2967
    );
  UUT_writeCount_share0000_14_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_14_XORF_2987,
      O => UUT_writeCount_share0000(14)
    );
  UUT_writeCount_share0000_14_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y7"
    )
    port map (
      I0 => UUT_writeCount_share0000_14_CYINIT_2986,
      I1 => UUT_writeCount_share0000_14_F,
      O => UUT_writeCount_share0000_14_XORF_2987
    );
  UUT_writeCount_share0000_14_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y7"
    )
    port map (
      IA => UUT_writeCount_share0000_14_LOGIC_ZERO_2967,
      IB => UUT_writeCount_share0000_14_CYINIT_2986,
      SEL => UUT_writeCount_share0000_14_CYSELF_2973,
      O => UUT_Madd_writeCount_share0000_cy(14)
    );
  UUT_writeCount_share0000_14_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y7"
    )
    port map (
      IA => UUT_writeCount_share0000_14_LOGIC_ZERO_2967,
      IB => UUT_writeCount_share0000_14_LOGIC_ZERO_2967,
      SEL => UUT_writeCount_share0000_14_CYSELF_2973,
      O => UUT_writeCount_share0000_14_CYMUXF2_2968
    );
  UUT_writeCount_share0000_14_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(13),
      O => UUT_writeCount_share0000_14_CYINIT_2986
    );
  UUT_writeCount_share0000_14_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_14_F,
      O => UUT_writeCount_share0000_14_CYSELF_2973
    );
  UUT_writeCount_share0000_14_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_14_XORG_2975,
      O => UUT_writeCount_share0000(15)
    );
  UUT_writeCount_share0000_14_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y7"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(14),
      I1 => UUT_writeCount_share0000_14_G,
      O => UUT_writeCount_share0000_14_XORG_2975
    );
  UUT_writeCount_share0000_14_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_14_CYMUXFAST_2972,
      O => UUT_Madd_writeCount_share0000_cy(15)
    );
  UUT_writeCount_share0000_14_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(13),
      O => UUT_writeCount_share0000_14_FASTCARRY_2970
    );
  UUT_writeCount_share0000_14_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y7"
    )
    port map (
      I0 => UUT_writeCount_share0000_14_CYSELG_2958,
      I1 => UUT_writeCount_share0000_14_CYSELF_2973,
      O => UUT_writeCount_share0000_14_CYAND_2971
    );
  UUT_writeCount_share0000_14_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y7"
    )
    port map (
      IA => UUT_writeCount_share0000_14_CYMUXG2_2969,
      IB => UUT_writeCount_share0000_14_FASTCARRY_2970,
      SEL => UUT_writeCount_share0000_14_CYAND_2971,
      O => UUT_writeCount_share0000_14_CYMUXFAST_2972
    );
  UUT_writeCount_share0000_14_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y7"
    )
    port map (
      IA => UUT_writeCount_share0000_14_LOGIC_ZERO_2967,
      IB => UUT_writeCount_share0000_14_CYMUXF2_2968,
      SEL => UUT_writeCount_share0000_14_CYSELG_2958,
      O => UUT_writeCount_share0000_14_CYMUXG2_2969
    );
  UUT_writeCount_share0000_14_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_14_G,
      O => UUT_writeCount_share0000_14_CYSELG_2958
    );
  UUT_writeCount_share0000_16_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y8"
    )
    port map (
      O => UUT_writeCount_share0000_16_LOGIC_ZERO_3005
    );
  UUT_writeCount_share0000_16_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_16_XORF_3025,
      O => UUT_writeCount_share0000(16)
    );
  UUT_writeCount_share0000_16_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y8"
    )
    port map (
      I0 => UUT_writeCount_share0000_16_CYINIT_3024,
      I1 => UUT_writeCount_share0000_16_F,
      O => UUT_writeCount_share0000_16_XORF_3025
    );
  UUT_writeCount_share0000_16_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y8"
    )
    port map (
      IA => UUT_writeCount_share0000_16_LOGIC_ZERO_3005,
      IB => UUT_writeCount_share0000_16_CYINIT_3024,
      SEL => UUT_writeCount_share0000_16_CYSELF_3011,
      O => UUT_Madd_writeCount_share0000_cy(16)
    );
  UUT_writeCount_share0000_16_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y8"
    )
    port map (
      IA => UUT_writeCount_share0000_16_LOGIC_ZERO_3005,
      IB => UUT_writeCount_share0000_16_LOGIC_ZERO_3005,
      SEL => UUT_writeCount_share0000_16_CYSELF_3011,
      O => UUT_writeCount_share0000_16_CYMUXF2_3006
    );
  UUT_writeCount_share0000_16_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(15),
      O => UUT_writeCount_share0000_16_CYINIT_3024
    );
  UUT_writeCount_share0000_16_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_16_F,
      O => UUT_writeCount_share0000_16_CYSELF_3011
    );
  UUT_writeCount_share0000_16_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_16_XORG_3013,
      O => UUT_writeCount_share0000(17)
    );
  UUT_writeCount_share0000_16_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y8"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(16),
      I1 => UUT_writeCount_share0000_16_G,
      O => UUT_writeCount_share0000_16_XORG_3013
    );
  UUT_writeCount_share0000_16_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_16_CYMUXFAST_3010,
      O => UUT_Madd_writeCount_share0000_cy(17)
    );
  UUT_writeCount_share0000_16_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(15),
      O => UUT_writeCount_share0000_16_FASTCARRY_3008
    );
  UUT_writeCount_share0000_16_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y8"
    )
    port map (
      I0 => UUT_writeCount_share0000_16_CYSELG_2996,
      I1 => UUT_writeCount_share0000_16_CYSELF_3011,
      O => UUT_writeCount_share0000_16_CYAND_3009
    );
  UUT_writeCount_share0000_16_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y8"
    )
    port map (
      IA => UUT_writeCount_share0000_16_CYMUXG2_3007,
      IB => UUT_writeCount_share0000_16_FASTCARRY_3008,
      SEL => UUT_writeCount_share0000_16_CYAND_3009,
      O => UUT_writeCount_share0000_16_CYMUXFAST_3010
    );
  UUT_writeCount_share0000_16_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y8"
    )
    port map (
      IA => UUT_writeCount_share0000_16_LOGIC_ZERO_3005,
      IB => UUT_writeCount_share0000_16_CYMUXF2_3006,
      SEL => UUT_writeCount_share0000_16_CYSELG_2996,
      O => UUT_writeCount_share0000_16_CYMUXG2_3007
    );
  UUT_writeCount_share0000_16_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_16_G,
      O => UUT_writeCount_share0000_16_CYSELG_2996
    );
  UUT_writeCount_share0000_18_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y9"
    )
    port map (
      O => UUT_writeCount_share0000_18_LOGIC_ZERO_3043
    );
  UUT_writeCount_share0000_18_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_18_XORF_3063,
      O => UUT_writeCount_share0000(18)
    );
  UUT_writeCount_share0000_18_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y9"
    )
    port map (
      I0 => UUT_writeCount_share0000_18_CYINIT_3062,
      I1 => UUT_writeCount_share0000_18_F,
      O => UUT_writeCount_share0000_18_XORF_3063
    );
  UUT_writeCount_share0000_18_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y9"
    )
    port map (
      IA => UUT_writeCount_share0000_18_LOGIC_ZERO_3043,
      IB => UUT_writeCount_share0000_18_CYINIT_3062,
      SEL => UUT_writeCount_share0000_18_CYSELF_3049,
      O => UUT_Madd_writeCount_share0000_cy(18)
    );
  UUT_writeCount_share0000_18_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y9"
    )
    port map (
      IA => UUT_writeCount_share0000_18_LOGIC_ZERO_3043,
      IB => UUT_writeCount_share0000_18_LOGIC_ZERO_3043,
      SEL => UUT_writeCount_share0000_18_CYSELF_3049,
      O => UUT_writeCount_share0000_18_CYMUXF2_3044
    );
  UUT_writeCount_share0000_18_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(17),
      O => UUT_writeCount_share0000_18_CYINIT_3062
    );
  UUT_writeCount_share0000_18_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_18_F,
      O => UUT_writeCount_share0000_18_CYSELF_3049
    );
  UUT_writeCount_share0000_18_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_18_XORG_3051,
      O => UUT_writeCount_share0000(19)
    );
  UUT_writeCount_share0000_18_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y9"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(18),
      I1 => UUT_writeCount_share0000_18_G,
      O => UUT_writeCount_share0000_18_XORG_3051
    );
  UUT_writeCount_share0000_18_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_18_CYMUXFAST_3048,
      O => UUT_Madd_writeCount_share0000_cy(19)
    );
  UUT_writeCount_share0000_18_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(17),
      O => UUT_writeCount_share0000_18_FASTCARRY_3046
    );
  UUT_writeCount_share0000_18_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y9"
    )
    port map (
      I0 => UUT_writeCount_share0000_18_CYSELG_3034,
      I1 => UUT_writeCount_share0000_18_CYSELF_3049,
      O => UUT_writeCount_share0000_18_CYAND_3047
    );
  UUT_writeCount_share0000_18_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y9"
    )
    port map (
      IA => UUT_writeCount_share0000_18_CYMUXG2_3045,
      IB => UUT_writeCount_share0000_18_FASTCARRY_3046,
      SEL => UUT_writeCount_share0000_18_CYAND_3047,
      O => UUT_writeCount_share0000_18_CYMUXFAST_3048
    );
  UUT_writeCount_share0000_18_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y9"
    )
    port map (
      IA => UUT_writeCount_share0000_18_LOGIC_ZERO_3043,
      IB => UUT_writeCount_share0000_18_CYMUXF2_3044,
      SEL => UUT_writeCount_share0000_18_CYSELG_3034,
      O => UUT_writeCount_share0000_18_CYMUXG2_3045
    );
  UUT_writeCount_share0000_18_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_18_G,
      O => UUT_writeCount_share0000_18_CYSELG_3034
    );
  UUT_writeCount_share0000_20_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y10"
    )
    port map (
      O => UUT_writeCount_share0000_20_LOGIC_ZERO_3081
    );
  UUT_writeCount_share0000_20_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_20_XORF_3101,
      O => UUT_writeCount_share0000(20)
    );
  UUT_writeCount_share0000_20_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y10"
    )
    port map (
      I0 => UUT_writeCount_share0000_20_CYINIT_3100,
      I1 => UUT_writeCount_share0000_20_F,
      O => UUT_writeCount_share0000_20_XORF_3101
    );
  UUT_writeCount_share0000_20_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y10"
    )
    port map (
      IA => UUT_writeCount_share0000_20_LOGIC_ZERO_3081,
      IB => UUT_writeCount_share0000_20_CYINIT_3100,
      SEL => UUT_writeCount_share0000_20_CYSELF_3087,
      O => UUT_Madd_writeCount_share0000_cy(20)
    );
  UUT_writeCount_share0000_20_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y10"
    )
    port map (
      IA => UUT_writeCount_share0000_20_LOGIC_ZERO_3081,
      IB => UUT_writeCount_share0000_20_LOGIC_ZERO_3081,
      SEL => UUT_writeCount_share0000_20_CYSELF_3087,
      O => UUT_writeCount_share0000_20_CYMUXF2_3082
    );
  UUT_writeCount_share0000_20_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(19),
      O => UUT_writeCount_share0000_20_CYINIT_3100
    );
  UUT_writeCount_share0000_20_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_20_F,
      O => UUT_writeCount_share0000_20_CYSELF_3087
    );
  UUT_writeCount_share0000_20_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_20_XORG_3089,
      O => UUT_writeCount_share0000(21)
    );
  UUT_writeCount_share0000_20_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y10"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(20),
      I1 => UUT_writeCount_share0000_20_G,
      O => UUT_writeCount_share0000_20_XORG_3089
    );
  UUT_writeCount_share0000_20_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_20_CYMUXFAST_3086,
      O => UUT_Madd_writeCount_share0000_cy(21)
    );
  UUT_writeCount_share0000_20_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(19),
      O => UUT_writeCount_share0000_20_FASTCARRY_3084
    );
  UUT_writeCount_share0000_20_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y10"
    )
    port map (
      I0 => UUT_writeCount_share0000_20_CYSELG_3072,
      I1 => UUT_writeCount_share0000_20_CYSELF_3087,
      O => UUT_writeCount_share0000_20_CYAND_3085
    );
  UUT_writeCount_share0000_20_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y10"
    )
    port map (
      IA => UUT_writeCount_share0000_20_CYMUXG2_3083,
      IB => UUT_writeCount_share0000_20_FASTCARRY_3084,
      SEL => UUT_writeCount_share0000_20_CYAND_3085,
      O => UUT_writeCount_share0000_20_CYMUXFAST_3086
    );
  UUT_writeCount_share0000_20_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y10"
    )
    port map (
      IA => UUT_writeCount_share0000_20_LOGIC_ZERO_3081,
      IB => UUT_writeCount_share0000_20_CYMUXF2_3082,
      SEL => UUT_writeCount_share0000_20_CYSELG_3072,
      O => UUT_writeCount_share0000_20_CYMUXG2_3083
    );
  UUT_writeCount_share0000_20_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_20_G,
      O => UUT_writeCount_share0000_20_CYSELG_3072
    );
  UUT_writeCount_share0000_22_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y11"
    )
    port map (
      O => UUT_writeCount_share0000_22_LOGIC_ZERO_3119
    );
  UUT_writeCount_share0000_22_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_22_XORF_3139,
      O => UUT_writeCount_share0000(22)
    );
  UUT_writeCount_share0000_22_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y11"
    )
    port map (
      I0 => UUT_writeCount_share0000_22_CYINIT_3138,
      I1 => UUT_writeCount_share0000_22_F,
      O => UUT_writeCount_share0000_22_XORF_3139
    );
  UUT_writeCount_share0000_22_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y11"
    )
    port map (
      IA => UUT_writeCount_share0000_22_LOGIC_ZERO_3119,
      IB => UUT_writeCount_share0000_22_CYINIT_3138,
      SEL => UUT_writeCount_share0000_22_CYSELF_3125,
      O => UUT_Madd_writeCount_share0000_cy(22)
    );
  UUT_writeCount_share0000_22_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y11"
    )
    port map (
      IA => UUT_writeCount_share0000_22_LOGIC_ZERO_3119,
      IB => UUT_writeCount_share0000_22_LOGIC_ZERO_3119,
      SEL => UUT_writeCount_share0000_22_CYSELF_3125,
      O => UUT_writeCount_share0000_22_CYMUXF2_3120
    );
  UUT_writeCount_share0000_22_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(21),
      O => UUT_writeCount_share0000_22_CYINIT_3138
    );
  UUT_writeCount_share0000_22_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_22_F,
      O => UUT_writeCount_share0000_22_CYSELF_3125
    );
  UUT_writeCount_share0000_22_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_22_XORG_3127,
      O => UUT_writeCount_share0000(23)
    );
  UUT_writeCount_share0000_22_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y11"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(22),
      I1 => UUT_writeCount_share0000_22_G,
      O => UUT_writeCount_share0000_22_XORG_3127
    );
  UUT_writeCount_share0000_22_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_22_CYMUXFAST_3124,
      O => UUT_Madd_writeCount_share0000_cy(23)
    );
  UUT_writeCount_share0000_22_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(21),
      O => UUT_writeCount_share0000_22_FASTCARRY_3122
    );
  UUT_writeCount_share0000_22_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y11"
    )
    port map (
      I0 => UUT_writeCount_share0000_22_CYSELG_3110,
      I1 => UUT_writeCount_share0000_22_CYSELF_3125,
      O => UUT_writeCount_share0000_22_CYAND_3123
    );
  UUT_writeCount_share0000_22_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y11"
    )
    port map (
      IA => UUT_writeCount_share0000_22_CYMUXG2_3121,
      IB => UUT_writeCount_share0000_22_FASTCARRY_3122,
      SEL => UUT_writeCount_share0000_22_CYAND_3123,
      O => UUT_writeCount_share0000_22_CYMUXFAST_3124
    );
  UUT_writeCount_share0000_22_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y11"
    )
    port map (
      IA => UUT_writeCount_share0000_22_LOGIC_ZERO_3119,
      IB => UUT_writeCount_share0000_22_CYMUXF2_3120,
      SEL => UUT_writeCount_share0000_22_CYSELG_3110,
      O => UUT_writeCount_share0000_22_CYMUXG2_3121
    );
  UUT_writeCount_share0000_22_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_22_G,
      O => UUT_writeCount_share0000_22_CYSELG_3110
    );
  UUT_writeCount_share0000_24_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y12"
    )
    port map (
      O => UUT_writeCount_share0000_24_LOGIC_ZERO_3157
    );
  UUT_writeCount_share0000_24_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_24_XORF_3177,
      O => UUT_writeCount_share0000(24)
    );
  UUT_writeCount_share0000_24_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y12"
    )
    port map (
      I0 => UUT_writeCount_share0000_24_CYINIT_3176,
      I1 => UUT_writeCount_share0000_24_F,
      O => UUT_writeCount_share0000_24_XORF_3177
    );
  UUT_writeCount_share0000_24_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y12"
    )
    port map (
      IA => UUT_writeCount_share0000_24_LOGIC_ZERO_3157,
      IB => UUT_writeCount_share0000_24_CYINIT_3176,
      SEL => UUT_writeCount_share0000_24_CYSELF_3163,
      O => UUT_Madd_writeCount_share0000_cy(24)
    );
  UUT_writeCount_share0000_24_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y12"
    )
    port map (
      IA => UUT_writeCount_share0000_24_LOGIC_ZERO_3157,
      IB => UUT_writeCount_share0000_24_LOGIC_ZERO_3157,
      SEL => UUT_writeCount_share0000_24_CYSELF_3163,
      O => UUT_writeCount_share0000_24_CYMUXF2_3158
    );
  UUT_writeCount_share0000_24_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(23),
      O => UUT_writeCount_share0000_24_CYINIT_3176
    );
  UUT_writeCount_share0000_24_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_24_F,
      O => UUT_writeCount_share0000_24_CYSELF_3163
    );
  UUT_writeCount_share0000_24_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_24_XORG_3165,
      O => UUT_writeCount_share0000(25)
    );
  UUT_writeCount_share0000_24_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y12"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(24),
      I1 => UUT_writeCount_share0000_24_G,
      O => UUT_writeCount_share0000_24_XORG_3165
    );
  UUT_writeCount_share0000_24_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_24_CYMUXFAST_3162,
      O => UUT_Madd_writeCount_share0000_cy(25)
    );
  UUT_writeCount_share0000_24_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(23),
      O => UUT_writeCount_share0000_24_FASTCARRY_3160
    );
  UUT_writeCount_share0000_24_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y12"
    )
    port map (
      I0 => UUT_writeCount_share0000_24_CYSELG_3148,
      I1 => UUT_writeCount_share0000_24_CYSELF_3163,
      O => UUT_writeCount_share0000_24_CYAND_3161
    );
  UUT_writeCount_share0000_24_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y12"
    )
    port map (
      IA => UUT_writeCount_share0000_24_CYMUXG2_3159,
      IB => UUT_writeCount_share0000_24_FASTCARRY_3160,
      SEL => UUT_writeCount_share0000_24_CYAND_3161,
      O => UUT_writeCount_share0000_24_CYMUXFAST_3162
    );
  UUT_writeCount_share0000_24_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y12"
    )
    port map (
      IA => UUT_writeCount_share0000_24_LOGIC_ZERO_3157,
      IB => UUT_writeCount_share0000_24_CYMUXF2_3158,
      SEL => UUT_writeCount_share0000_24_CYSELG_3148,
      O => UUT_writeCount_share0000_24_CYMUXG2_3159
    );
  UUT_writeCount_share0000_24_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_24_G,
      O => UUT_writeCount_share0000_24_CYSELG_3148
    );
  UUT_writeCount_share0000_26_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y13"
    )
    port map (
      O => UUT_writeCount_share0000_26_LOGIC_ZERO_3195
    );
  UUT_writeCount_share0000_26_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_26_XORF_3215,
      O => UUT_writeCount_share0000(26)
    );
  UUT_writeCount_share0000_26_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y13"
    )
    port map (
      I0 => UUT_writeCount_share0000_26_CYINIT_3214,
      I1 => UUT_writeCount_share0000_26_F,
      O => UUT_writeCount_share0000_26_XORF_3215
    );
  UUT_writeCount_share0000_26_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y13"
    )
    port map (
      IA => UUT_writeCount_share0000_26_LOGIC_ZERO_3195,
      IB => UUT_writeCount_share0000_26_CYINIT_3214,
      SEL => UUT_writeCount_share0000_26_CYSELF_3201,
      O => UUT_Madd_writeCount_share0000_cy(26)
    );
  UUT_writeCount_share0000_26_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y13"
    )
    port map (
      IA => UUT_writeCount_share0000_26_LOGIC_ZERO_3195,
      IB => UUT_writeCount_share0000_26_LOGIC_ZERO_3195,
      SEL => UUT_writeCount_share0000_26_CYSELF_3201,
      O => UUT_writeCount_share0000_26_CYMUXF2_3196
    );
  UUT_writeCount_share0000_26_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(25),
      O => UUT_writeCount_share0000_26_CYINIT_3214
    );
  UUT_writeCount_share0000_26_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_26_F,
      O => UUT_writeCount_share0000_26_CYSELF_3201
    );
  UUT_writeCount_share0000_26_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_26_XORG_3203,
      O => UUT_writeCount_share0000(27)
    );
  UUT_writeCount_share0000_26_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y13"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(26),
      I1 => UUT_writeCount_share0000_26_G,
      O => UUT_writeCount_share0000_26_XORG_3203
    );
  UUT_writeCount_share0000_26_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_26_CYMUXFAST_3200,
      O => UUT_Madd_writeCount_share0000_cy(27)
    );
  UUT_writeCount_share0000_26_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(25),
      O => UUT_writeCount_share0000_26_FASTCARRY_3198
    );
  UUT_writeCount_share0000_26_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y13"
    )
    port map (
      I0 => UUT_writeCount_share0000_26_CYSELG_3186,
      I1 => UUT_writeCount_share0000_26_CYSELF_3201,
      O => UUT_writeCount_share0000_26_CYAND_3199
    );
  UUT_writeCount_share0000_26_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y13"
    )
    port map (
      IA => UUT_writeCount_share0000_26_CYMUXG2_3197,
      IB => UUT_writeCount_share0000_26_FASTCARRY_3198,
      SEL => UUT_writeCount_share0000_26_CYAND_3199,
      O => UUT_writeCount_share0000_26_CYMUXFAST_3200
    );
  UUT_writeCount_share0000_26_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y13"
    )
    port map (
      IA => UUT_writeCount_share0000_26_LOGIC_ZERO_3195,
      IB => UUT_writeCount_share0000_26_CYMUXF2_3196,
      SEL => UUT_writeCount_share0000_26_CYSELG_3186,
      O => UUT_writeCount_share0000_26_CYMUXG2_3197
    );
  UUT_writeCount_share0000_26_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_26_G,
      O => UUT_writeCount_share0000_26_CYSELG_3186
    );
  UUT_writeCount_share0000_0_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y0"
    )
    port map (
      O => UUT_writeCount_share0000_0_LOGIC_ZERO_2703
    );
  UUT_writeCount_share0000_0_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X37Y0"
    )
    port map (
      O => UUT_writeCount_share0000_0_LOGIC_ONE_2720
    );
  UUT_writeCount_share0000_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_0_XORF_2721,
      O => UUT_writeCount_share0000(0)
    );
  UUT_writeCount_share0000_0_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y0"
    )
    port map (
      I0 => UUT_writeCount_share0000_0_CYINIT_2719,
      I1 => UUT_Madd_writeCount_share0000_lut(0),
      O => UUT_writeCount_share0000_0_XORF_2721
    );
  UUT_writeCount_share0000_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y0"
    )
    port map (
      IA => UUT_writeCount_share0000_0_LOGIC_ONE_2720,
      IB => UUT_writeCount_share0000_0_CYINIT_2719,
      SEL => UUT_writeCount_share0000_0_CYSELF_2710,
      O => UUT_Madd_writeCount_share0000_cy(0)
    );
  UUT_writeCount_share0000_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => UUT_writeCount_share0000_0_CYINIT_2719
    );
  UUT_writeCount_share0000_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_lut(0),
      O => UUT_writeCount_share0000_0_CYSELF_2710
    );
  UUT_writeCount_share0000_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_0_XORG_2706,
      O => UUT_writeCount_share0000(1)
    );
  UUT_writeCount_share0000_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y0"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(0),
      I1 => UUT_writeCount_share0000_0_G,
      O => UUT_writeCount_share0000_0_XORG_2706
    );
  UUT_writeCount_share0000_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_0_CYMUXG_2705,
      O => UUT_Madd_writeCount_share0000_cy(1)
    );
  UUT_writeCount_share0000_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X37Y0"
    )
    port map (
      IA => UUT_writeCount_share0000_0_LOGIC_ZERO_2703,
      IB => UUT_Madd_writeCount_share0000_cy(0),
      SEL => UUT_writeCount_share0000_0_CYSELG_2694,
      O => UUT_writeCount_share0000_0_CYMUXG_2705
    );
  UUT_writeCount_share0000_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_0_G,
      O => UUT_writeCount_share0000_0_CYSELG_2694
    );
  UUT_writeCount_share0000_2_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y1"
    )
    port map (
      O => UUT_writeCount_share0000_2_LOGIC_ZERO_2739
    );
  UUT_writeCount_share0000_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_2_XORF_2759,
      O => UUT_writeCount_share0000(2)
    );
  UUT_writeCount_share0000_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y1"
    )
    port map (
      I0 => UUT_writeCount_share0000_2_CYINIT_2758,
      I1 => UUT_writeCount_share0000_2_F,
      O => UUT_writeCount_share0000_2_XORF_2759
    );
  UUT_writeCount_share0000_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y1"
    )
    port map (
      IA => UUT_writeCount_share0000_2_LOGIC_ZERO_2739,
      IB => UUT_writeCount_share0000_2_CYINIT_2758,
      SEL => UUT_writeCount_share0000_2_CYSELF_2745,
      O => UUT_Madd_writeCount_share0000_cy(2)
    );
  UUT_writeCount_share0000_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y1"
    )
    port map (
      IA => UUT_writeCount_share0000_2_LOGIC_ZERO_2739,
      IB => UUT_writeCount_share0000_2_LOGIC_ZERO_2739,
      SEL => UUT_writeCount_share0000_2_CYSELF_2745,
      O => UUT_writeCount_share0000_2_CYMUXF2_2740
    );
  UUT_writeCount_share0000_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(1),
      O => UUT_writeCount_share0000_2_CYINIT_2758
    );
  UUT_writeCount_share0000_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_2_F,
      O => UUT_writeCount_share0000_2_CYSELF_2745
    );
  UUT_writeCount_share0000_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_2_XORG_2747,
      O => UUT_writeCount_share0000(3)
    );
  UUT_writeCount_share0000_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y1"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(2),
      I1 => UUT_writeCount_share0000_2_G,
      O => UUT_writeCount_share0000_2_XORG_2747
    );
  UUT_writeCount_share0000_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_2_CYMUXFAST_2744,
      O => UUT_Madd_writeCount_share0000_cy(3)
    );
  UUT_writeCount_share0000_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(1),
      O => UUT_writeCount_share0000_2_FASTCARRY_2742
    );
  UUT_writeCount_share0000_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y1"
    )
    port map (
      I0 => UUT_writeCount_share0000_2_CYSELG_2730,
      I1 => UUT_writeCount_share0000_2_CYSELF_2745,
      O => UUT_writeCount_share0000_2_CYAND_2743
    );
  UUT_writeCount_share0000_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y1"
    )
    port map (
      IA => UUT_writeCount_share0000_2_CYMUXG2_2741,
      IB => UUT_writeCount_share0000_2_FASTCARRY_2742,
      SEL => UUT_writeCount_share0000_2_CYAND_2743,
      O => UUT_writeCount_share0000_2_CYMUXFAST_2744
    );
  UUT_writeCount_share0000_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y1"
    )
    port map (
      IA => UUT_writeCount_share0000_2_LOGIC_ZERO_2739,
      IB => UUT_writeCount_share0000_2_CYMUXF2_2740,
      SEL => UUT_writeCount_share0000_2_CYSELG_2730,
      O => UUT_writeCount_share0000_2_CYMUXG2_2741
    );
  UUT_writeCount_share0000_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_2_G,
      O => UUT_writeCount_share0000_2_CYSELG_2730
    );
  UUT_writeCount_share0000_4_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y2"
    )
    port map (
      O => UUT_writeCount_share0000_4_LOGIC_ZERO_2777
    );
  UUT_writeCount_share0000_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_4_XORF_2797,
      O => UUT_writeCount_share0000(4)
    );
  UUT_writeCount_share0000_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y2"
    )
    port map (
      I0 => UUT_writeCount_share0000_4_CYINIT_2796,
      I1 => UUT_writeCount_share0000_4_F,
      O => UUT_writeCount_share0000_4_XORF_2797
    );
  UUT_writeCount_share0000_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y2"
    )
    port map (
      IA => UUT_writeCount_share0000_4_LOGIC_ZERO_2777,
      IB => UUT_writeCount_share0000_4_CYINIT_2796,
      SEL => UUT_writeCount_share0000_4_CYSELF_2783,
      O => UUT_Madd_writeCount_share0000_cy(4)
    );
  UUT_writeCount_share0000_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y2"
    )
    port map (
      IA => UUT_writeCount_share0000_4_LOGIC_ZERO_2777,
      IB => UUT_writeCount_share0000_4_LOGIC_ZERO_2777,
      SEL => UUT_writeCount_share0000_4_CYSELF_2783,
      O => UUT_writeCount_share0000_4_CYMUXF2_2778
    );
  UUT_writeCount_share0000_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(3),
      O => UUT_writeCount_share0000_4_CYINIT_2796
    );
  UUT_writeCount_share0000_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_4_F,
      O => UUT_writeCount_share0000_4_CYSELF_2783
    );
  UUT_writeCount_share0000_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_4_XORG_2785,
      O => UUT_writeCount_share0000(5)
    );
  UUT_writeCount_share0000_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y2"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(4),
      I1 => UUT_writeCount_share0000_4_G,
      O => UUT_writeCount_share0000_4_XORG_2785
    );
  UUT_writeCount_share0000_4_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_4_CYMUXFAST_2782,
      O => UUT_Madd_writeCount_share0000_cy(5)
    );
  UUT_writeCount_share0000_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(3),
      O => UUT_writeCount_share0000_4_FASTCARRY_2780
    );
  UUT_writeCount_share0000_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y2"
    )
    port map (
      I0 => UUT_writeCount_share0000_4_CYSELG_2768,
      I1 => UUT_writeCount_share0000_4_CYSELF_2783,
      O => UUT_writeCount_share0000_4_CYAND_2781
    );
  UUT_writeCount_share0000_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y2"
    )
    port map (
      IA => UUT_writeCount_share0000_4_CYMUXG2_2779,
      IB => UUT_writeCount_share0000_4_FASTCARRY_2780,
      SEL => UUT_writeCount_share0000_4_CYAND_2781,
      O => UUT_writeCount_share0000_4_CYMUXFAST_2782
    );
  UUT_writeCount_share0000_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y2"
    )
    port map (
      IA => UUT_writeCount_share0000_4_LOGIC_ZERO_2777,
      IB => UUT_writeCount_share0000_4_CYMUXF2_2778,
      SEL => UUT_writeCount_share0000_4_CYSELG_2768,
      O => UUT_writeCount_share0000_4_CYMUXG2_2779
    );
  UUT_writeCount_share0000_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_4_G,
      O => UUT_writeCount_share0000_4_CYSELG_2768
    );
  UUT_writeCount_share0000_6_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y3"
    )
    port map (
      O => UUT_writeCount_share0000_6_LOGIC_ZERO_2815
    );
  UUT_writeCount_share0000_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_6_XORF_2835,
      O => UUT_writeCount_share0000(6)
    );
  UUT_writeCount_share0000_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y3"
    )
    port map (
      I0 => UUT_writeCount_share0000_6_CYINIT_2834,
      I1 => UUT_writeCount_share0000_6_F,
      O => UUT_writeCount_share0000_6_XORF_2835
    );
  UUT_writeCount_share0000_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y3"
    )
    port map (
      IA => UUT_writeCount_share0000_6_LOGIC_ZERO_2815,
      IB => UUT_writeCount_share0000_6_CYINIT_2834,
      SEL => UUT_writeCount_share0000_6_CYSELF_2821,
      O => UUT_Madd_writeCount_share0000_cy(6)
    );
  UUT_writeCount_share0000_6_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y3"
    )
    port map (
      IA => UUT_writeCount_share0000_6_LOGIC_ZERO_2815,
      IB => UUT_writeCount_share0000_6_LOGIC_ZERO_2815,
      SEL => UUT_writeCount_share0000_6_CYSELF_2821,
      O => UUT_writeCount_share0000_6_CYMUXF2_2816
    );
  UUT_writeCount_share0000_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(5),
      O => UUT_writeCount_share0000_6_CYINIT_2834
    );
  UUT_writeCount_share0000_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_6_F,
      O => UUT_writeCount_share0000_6_CYSELF_2821
    );
  UUT_writeCount_share0000_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_6_XORG_2823,
      O => UUT_writeCount_share0000(7)
    );
  UUT_writeCount_share0000_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y3"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(6),
      I1 => UUT_writeCount_share0000_6_G,
      O => UUT_writeCount_share0000_6_XORG_2823
    );
  UUT_writeCount_share0000_6_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_6_CYMUXFAST_2820,
      O => UUT_Madd_writeCount_share0000_cy(7)
    );
  UUT_writeCount_share0000_6_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(5),
      O => UUT_writeCount_share0000_6_FASTCARRY_2818
    );
  UUT_writeCount_share0000_6_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y3"
    )
    port map (
      I0 => UUT_writeCount_share0000_6_CYSELG_2806,
      I1 => UUT_writeCount_share0000_6_CYSELF_2821,
      O => UUT_writeCount_share0000_6_CYAND_2819
    );
  UUT_writeCount_share0000_6_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y3"
    )
    port map (
      IA => UUT_writeCount_share0000_6_CYMUXG2_2817,
      IB => UUT_writeCount_share0000_6_FASTCARRY_2818,
      SEL => UUT_writeCount_share0000_6_CYAND_2819,
      O => UUT_writeCount_share0000_6_CYMUXFAST_2820
    );
  UUT_writeCount_share0000_6_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y3"
    )
    port map (
      IA => UUT_writeCount_share0000_6_LOGIC_ZERO_2815,
      IB => UUT_writeCount_share0000_6_CYMUXF2_2816,
      SEL => UUT_writeCount_share0000_6_CYSELG_2806,
      O => UUT_writeCount_share0000_6_CYMUXG2_2817
    );
  UUT_writeCount_share0000_6_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_6_G,
      O => UUT_writeCount_share0000_6_CYSELG_2806
    );
  UUT_writeCount_share0000_8_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X37Y4"
    )
    port map (
      O => UUT_writeCount_share0000_8_LOGIC_ZERO_2853
    );
  UUT_writeCount_share0000_8_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_8_XORF_2873,
      O => UUT_writeCount_share0000(8)
    );
  UUT_writeCount_share0000_8_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X37Y4"
    )
    port map (
      I0 => UUT_writeCount_share0000_8_CYINIT_2872,
      I1 => UUT_writeCount_share0000_8_F,
      O => UUT_writeCount_share0000_8_XORF_2873
    );
  UUT_writeCount_share0000_8_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y4"
    )
    port map (
      IA => UUT_writeCount_share0000_8_LOGIC_ZERO_2853,
      IB => UUT_writeCount_share0000_8_CYINIT_2872,
      SEL => UUT_writeCount_share0000_8_CYSELF_2859,
      O => UUT_Madd_writeCount_share0000_cy(8)
    );
  UUT_writeCount_share0000_8_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y4"
    )
    port map (
      IA => UUT_writeCount_share0000_8_LOGIC_ZERO_2853,
      IB => UUT_writeCount_share0000_8_LOGIC_ZERO_2853,
      SEL => UUT_writeCount_share0000_8_CYSELF_2859,
      O => UUT_writeCount_share0000_8_CYMUXF2_2854
    );
  UUT_writeCount_share0000_8_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(7),
      O => UUT_writeCount_share0000_8_CYINIT_2872
    );
  UUT_writeCount_share0000_8_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_8_F,
      O => UUT_writeCount_share0000_8_CYSELF_2859
    );
  UUT_writeCount_share0000_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_8_XORG_2861,
      O => UUT_writeCount_share0000(9)
    );
  UUT_writeCount_share0000_8_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X37Y4"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(8),
      I1 => UUT_writeCount_share0000_8_G,
      O => UUT_writeCount_share0000_8_XORG_2861
    );
  UUT_writeCount_share0000_8_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_8_CYMUXFAST_2858,
      O => UUT_Madd_writeCount_share0000_cy(9)
    );
  UUT_writeCount_share0000_8_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(7),
      O => UUT_writeCount_share0000_8_FASTCARRY_2856
    );
  UUT_writeCount_share0000_8_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y4"
    )
    port map (
      I0 => UUT_writeCount_share0000_8_CYSELG_2844,
      I1 => UUT_writeCount_share0000_8_CYSELF_2859,
      O => UUT_writeCount_share0000_8_CYAND_2857
    );
  UUT_writeCount_share0000_8_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y4"
    )
    port map (
      IA => UUT_writeCount_share0000_8_CYMUXG2_2855,
      IB => UUT_writeCount_share0000_8_FASTCARRY_2856,
      SEL => UUT_writeCount_share0000_8_CYAND_2857,
      O => UUT_writeCount_share0000_8_CYMUXFAST_2858
    );
  UUT_writeCount_share0000_8_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y4"
    )
    port map (
      IA => UUT_writeCount_share0000_8_LOGIC_ZERO_2853,
      IB => UUT_writeCount_share0000_8_CYMUXF2_2854,
      SEL => UUT_writeCount_share0000_8_CYSELG_2844,
      O => UUT_writeCount_share0000_8_CYMUXG2_2855
    );
  UUT_writeCount_share0000_8_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_8_G,
      O => UUT_writeCount_share0000_8_CYSELG_2844
    );
  CLK_clk_div_0_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X33Y32"
    )
    port map (
      O => CLK_clk_div_0_LOGIC_ZERO_4178
    );
  CLK_clk_div_0_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X33Y32"
    )
    port map (
      O => CLK_clk_div_0_LOGIC_ONE_4200
    );
  CLK_clk_div_0_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X33Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_0_XORF_4201,
      O => CLK_clk_div_0_DXMUX_4203
    );
  CLK_clk_div_0_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X33Y32"
    )
    port map (
      I0 => CLK_clk_div_0_CYINIT_4199,
      I1 => CLK_Mcount_clk_div_lut(0),
      O => CLK_clk_div_0_XORF_4201
    );
  CLK_clk_div_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X33Y32"
    )
    port map (
      IA => CLK_clk_div_0_LOGIC_ONE_4200,
      IB => CLK_clk_div_0_CYINIT_4199,
      SEL => CLK_clk_div_0_CYSELF_4190,
      O => CLK_Mcount_clk_div_cy_0_Q
    );
  CLK_clk_div_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X33Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => CLK_clk_div_0_CYINIT_4199
    );
  CLK_clk_div_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_Mcount_clk_div_lut(0),
      O => CLK_clk_div_0_CYSELF_4190
    );
  CLK_clk_div_0_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X33Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_0_XORG_4181,
      O => CLK_clk_div_0_DYMUX_4183
    );
  CLK_clk_div_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X33Y32"
    )
    port map (
      I0 => CLK_Mcount_clk_div_cy_0_Q,
      I1 => CLK_clk_div_0_G,
      O => CLK_clk_div_0_XORG_4181
    );
  CLK_clk_div_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_0_CYMUXG_4180,
      O => CLK_Mcount_clk_div_cy_1_Q
    );
  CLK_clk_div_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X33Y32"
    )
    port map (
      IA => CLK_clk_div_0_LOGIC_ZERO_4178,
      IB => CLK_Mcount_clk_div_cy_0_Q,
      SEL => CLK_clk_div_0_CYSELG_4169,
      O => CLK_clk_div_0_CYMUXG_4180
    );
  CLK_clk_div_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_0_G,
      O => CLK_clk_div_0_CYSELG_4169
    );
  CLK_clk_div_0_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X33Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq0000_0,
      O => CLK_clk_div_0_SRINV_4167
    );
  CLK_clk_div_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X33Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => CLK_clk_div_0_CLKINV_4166
    );
  CLK_clk_div_2_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X33Y33"
    )
    port map (
      O => CLK_clk_div_2_LOGIC_ZERO_4228
    );
  CLK_clk_div_2_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X33Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_2_XORF_4253,
      O => CLK_clk_div_2_DXMUX_4255
    );
  CLK_clk_div_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X33Y33"
    )
    port map (
      I0 => CLK_clk_div_2_CYINIT_4252,
      I1 => CLK_clk_div_2_F,
      O => CLK_clk_div_2_XORF_4253
    );
  CLK_clk_div_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X33Y33"
    )
    port map (
      IA => CLK_clk_div_2_LOGIC_ZERO_4228,
      IB => CLK_clk_div_2_CYINIT_4252,
      SEL => CLK_clk_div_2_CYSELF_4234,
      O => CLK_Mcount_clk_div_cy_2_Q
    );
  CLK_clk_div_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y33"
    )
    port map (
      IA => CLK_clk_div_2_LOGIC_ZERO_4228,
      IB => CLK_clk_div_2_LOGIC_ZERO_4228,
      SEL => CLK_clk_div_2_CYSELF_4234,
      O => CLK_clk_div_2_CYMUXF2_4229
    );
  CLK_clk_div_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X33Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_Mcount_clk_div_cy_1_Q,
      O => CLK_clk_div_2_CYINIT_4252
    );
  CLK_clk_div_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_2_F,
      O => CLK_clk_div_2_CYSELF_4234
    );
  CLK_clk_div_2_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X33Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_2_XORG_4236,
      O => CLK_clk_div_2_DYMUX_4238
    );
  CLK_clk_div_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X33Y33"
    )
    port map (
      I0 => CLK_Mcount_clk_div_cy_2_Q,
      I1 => CLK_clk_div_2_G,
      O => CLK_clk_div_2_XORG_4236
    );
  CLK_clk_div_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_2_CYMUXFAST_4233,
      O => CLK_Mcount_clk_div_cy_3_Q
    );
  CLK_clk_div_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X33Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_Mcount_clk_div_cy_1_Q,
      O => CLK_clk_div_2_FASTCARRY_4231
    );
  CLK_clk_div_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X33Y33"
    )
    port map (
      I0 => CLK_clk_div_2_CYSELG_4219,
      I1 => CLK_clk_div_2_CYSELF_4234,
      O => CLK_clk_div_2_CYAND_4232
    );
  CLK_clk_div_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X33Y33"
    )
    port map (
      IA => CLK_clk_div_2_CYMUXG2_4230,
      IB => CLK_clk_div_2_FASTCARRY_4231,
      SEL => CLK_clk_div_2_CYAND_4232,
      O => CLK_clk_div_2_CYMUXFAST_4233
    );
  CLK_clk_div_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y33"
    )
    port map (
      IA => CLK_clk_div_2_LOGIC_ZERO_4228,
      IB => CLK_clk_div_2_CYMUXF2_4229,
      SEL => CLK_clk_div_2_CYSELG_4219,
      O => CLK_clk_div_2_CYMUXG2_4230
    );
  CLK_clk_div_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_2_G,
      O => CLK_clk_div_2_CYSELG_4219
    );
  CLK_clk_div_2_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X33Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq0000_0,
      O => CLK_clk_div_2_SRINV_4217
    );
  CLK_clk_div_2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X33Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => CLK_clk_div_2_CLKINV_4216
    );
  CLK_clk_div_4_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X33Y34"
    )
    port map (
      O => CLK_clk_div_4_LOGIC_ZERO_4280
    );
  CLK_clk_div_4_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X33Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_4_XORF_4305,
      O => CLK_clk_div_4_DXMUX_4307
    );
  CLK_clk_div_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X33Y34"
    )
    port map (
      I0 => CLK_clk_div_4_CYINIT_4304,
      I1 => CLK_clk_div_4_F,
      O => CLK_clk_div_4_XORF_4305
    );
  CLK_clk_div_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X33Y34"
    )
    port map (
      IA => CLK_clk_div_4_LOGIC_ZERO_4280,
      IB => CLK_clk_div_4_CYINIT_4304,
      SEL => CLK_clk_div_4_CYSELF_4286,
      O => CLK_Mcount_clk_div_cy_4_Q
    );
  CLK_clk_div_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y34"
    )
    port map (
      IA => CLK_clk_div_4_LOGIC_ZERO_4280,
      IB => CLK_clk_div_4_LOGIC_ZERO_4280,
      SEL => CLK_clk_div_4_CYSELF_4286,
      O => CLK_clk_div_4_CYMUXF2_4281
    );
  CLK_clk_div_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X33Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_Mcount_clk_div_cy_3_Q,
      O => CLK_clk_div_4_CYINIT_4304
    );
  CLK_clk_div_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_4_F,
      O => CLK_clk_div_4_CYSELF_4286
    );
  CLK_clk_div_4_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X33Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_4_XORG_4288,
      O => CLK_clk_div_4_DYMUX_4290
    );
  CLK_clk_div_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X33Y34"
    )
    port map (
      I0 => CLK_Mcount_clk_div_cy_4_Q,
      I1 => CLK_clk_div_4_G,
      O => CLK_clk_div_4_XORG_4288
    );
  CLK_clk_div_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X33Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_Mcount_clk_div_cy_3_Q,
      O => CLK_clk_div_4_FASTCARRY_4283
    );
  CLK_clk_div_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X33Y34"
    )
    port map (
      I0 => CLK_clk_div_4_CYSELG_4271,
      I1 => CLK_clk_div_4_CYSELF_4286,
      O => CLK_clk_div_4_CYAND_4284
    );
  CLK_clk_div_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X33Y34"
    )
    port map (
      IA => CLK_clk_div_4_CYMUXG2_4282,
      IB => CLK_clk_div_4_FASTCARRY_4283,
      SEL => CLK_clk_div_4_CYAND_4284,
      O => CLK_clk_div_4_CYMUXFAST_4285
    );
  CLK_clk_div_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y34"
    )
    port map (
      IA => CLK_clk_div_4_LOGIC_ZERO_4280,
      IB => CLK_clk_div_4_CYMUXF2_4281,
      SEL => CLK_clk_div_4_CYSELG_4271,
      O => CLK_clk_div_4_CYMUXG2_4282
    );
  CLK_clk_div_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_4_G,
      O => CLK_clk_div_4_CYSELG_4271
    );
  CLK_clk_div_4_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X33Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq0000_0,
      O => CLK_clk_div_4_SRINV_4269
    );
  CLK_clk_div_4_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X33Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => CLK_clk_div_4_CLKINV_4268
    );
  CLK_clk_div_6_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X33Y35"
    )
    port map (
      O => CLK_clk_div_6_LOGIC_ZERO_4349
    );
  CLK_clk_div_6_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X33Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_6_XORF_4350,
      O => CLK_clk_div_6_DXMUX_4352
    );
  CLK_clk_div_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X33Y35"
    )
    port map (
      I0 => CLK_clk_div_6_CYINIT_4348,
      I1 => CLK_clk_div_6_F,
      O => CLK_clk_div_6_XORF_4350
    );
  CLK_clk_div_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X33Y35"
    )
    port map (
      IA => CLK_clk_div_6_LOGIC_ZERO_4349,
      IB => CLK_clk_div_6_CYINIT_4348,
      SEL => CLK_clk_div_6_CYSELF_4339,
      O => CLK_Mcount_clk_div_cy_6_Q
    );
  CLK_clk_div_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X33Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_4_CYMUXFAST_4285,
      O => CLK_clk_div_6_CYINIT_4348
    );
  CLK_clk_div_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_6_F,
      O => CLK_clk_div_6_CYSELF_4339
    );
  CLK_clk_div_6_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X33Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_6_XORG_4331,
      O => CLK_clk_div_6_DYMUX_4333
    );
  CLK_clk_div_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X33Y35"
    )
    port map (
      I0 => CLK_Mcount_clk_div_cy_6_Q,
      I1 => CLK_clk_div_7_rt_4328,
      O => CLK_clk_div_6_XORG_4331
    );
  CLK_clk_div_6_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X33Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq0000_0,
      O => CLK_clk_div_6_SRINV_4320
    );
  CLK_clk_div_6_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X33Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => CLK_clk_div_6_CLKINV_4319
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X21Y35"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ONE_4372
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y35"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ZERO_4386
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y35"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ZERO_4386,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYINIT_4385,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELF_4377,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_0_1
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYINIT_4385
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut_0_1_4376,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELF_4377
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X21Y35"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ONE_4372,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_0_1,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELG_4363,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYMUXG_4374
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_4_rt,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELG_4363
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X21Y36"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ONE_4401
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y36"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ZERO_4417
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y36"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ZERO_4417,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ZERO_4417,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELF_4407,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXF2_4402
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut_2_1,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELF_4407
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYMUXG_4374,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_FASTCARRY_4404
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y36"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELG_4393,
      I1 => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELF_4407,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYAND_4405
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y36"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXG2_4403,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_FASTCARRY_4404,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYAND_4405,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXFAST_4406
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y36"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ONE_4401,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXF2_4402,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELG_4393,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXG2_4403
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(3),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELG_4393
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X21Y37"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ONE_4432
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y37"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ZERO_4448
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y37"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ZERO_4448,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ZERO_4448,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELF_4438,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXF2_4433
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut_4_1,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELF_4438
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXFAST_4406,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_FASTCARRY_4435
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y37"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELG_4424,
      I1 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELF_4438,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYAND_4436
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y37"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXG2_4434,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_FASTCARRY_4435,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYAND_4436,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXFAST_4437
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y37"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ONE_4432,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXF2_4433,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELG_4424,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXG2_4434
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut_5_1_4423,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELG_4424
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y38"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_LOGIC_ZERO_4466
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y38"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_7_LOGIC_ZERO_4466,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_7_LOGIC_ZERO_4466,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELF_4472,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXF2_4467
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(6),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELF_4472
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXFAST_4471,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXFAST_4437,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_FASTCARRY_4469
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y38"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELG_4457,
      I1 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELF_4472,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYAND_4470
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y38"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXG2_4468,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_7_FASTCARRY_4469,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYAND_4470,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXFAST_4471
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y38"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_7_LOGIC_ZERO_4466,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXF2_4467,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELG_4457,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXG2_4468
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(7),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELG_4457
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X21Y32"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ONE_4495
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y32"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ZERO_4508
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y32"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ZERO_4508,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYINIT_4507,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELF_4500,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_0_Q
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYINIT_4507
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(0),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELF_4500
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X21Y32"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ONE_4495,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_0_Q,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELG_4487,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYMUXG_4497
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(1),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELG_4487
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X21Y33"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ONE_4523
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y33"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ZERO_4539
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y33"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ZERO_4539,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ZERO_4539,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELF_4529,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXF2_4524
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(2),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELF_4529
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYMUXG_4497,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_FASTCARRY_4526
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y33"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELG_4514,
      I1 => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELF_4529,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYAND_4527
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y33"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXG2_4525,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_3_FASTCARRY_4526,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYAND_4527,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXFAST_4528
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y33"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ONE_4523,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXF2_4524,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELG_4514,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXG2_4525
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_3_G,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELG_4514
    );
  UUT_delay_count_share0000_4_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      O => UUT_delay_count_share0000_4_LOGIC_ZERO_3865
    );
  UUT_delay_count_share0000_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_4_XORF_3885,
      O => UUT_delay_count_share0000(4)
    );
  UUT_delay_count_share0000_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      I0 => UUT_delay_count_share0000_4_CYINIT_3884,
      I1 => UUT_delay_count_share0000_4_F,
      O => UUT_delay_count_share0000_4_XORF_3885
    );
  UUT_delay_count_share0000_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      IA => UUT_delay_count_share0000_4_LOGIC_ZERO_3865,
      IB => UUT_delay_count_share0000_4_CYINIT_3884,
      SEL => UUT_delay_count_share0000_4_CYSELF_3871,
      O => UUT_Madd_delay_count_share0000_cy_4_Q
    );
  UUT_delay_count_share0000_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      IA => UUT_delay_count_share0000_4_LOGIC_ZERO_3865,
      IB => UUT_delay_count_share0000_4_LOGIC_ZERO_3865,
      SEL => UUT_delay_count_share0000_4_CYSELF_3871,
      O => UUT_delay_count_share0000_4_CYMUXF2_3866
    );
  UUT_delay_count_share0000_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_3_Q,
      O => UUT_delay_count_share0000_4_CYINIT_3884
    );
  UUT_delay_count_share0000_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_4_F,
      O => UUT_delay_count_share0000_4_CYSELF_3871
    );
  UUT_delay_count_share0000_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_4_XORG_3873,
      O => UUT_delay_count_share0000(5)
    );
  UUT_delay_count_share0000_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_4_Q,
      I1 => UUT_delay_count_share0000_4_G,
      O => UUT_delay_count_share0000_4_XORG_3873
    );
  UUT_delay_count_share0000_4_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_4_CYMUXFAST_3870,
      O => UUT_Madd_delay_count_share0000_cy_5_Q
    );
  UUT_delay_count_share0000_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_3_Q,
      O => UUT_delay_count_share0000_4_FASTCARRY_3868
    );
  UUT_delay_count_share0000_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      I0 => UUT_delay_count_share0000_4_CYSELG_3856,
      I1 => UUT_delay_count_share0000_4_CYSELF_3871,
      O => UUT_delay_count_share0000_4_CYAND_3869
    );
  UUT_delay_count_share0000_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      IA => UUT_delay_count_share0000_4_CYMUXG2_3867,
      IB => UUT_delay_count_share0000_4_FASTCARRY_3868,
      SEL => UUT_delay_count_share0000_4_CYAND_3869,
      O => UUT_delay_count_share0000_4_CYMUXFAST_3870
    );
  UUT_delay_count_share0000_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y22"
    )
    port map (
      IA => UUT_delay_count_share0000_4_LOGIC_ZERO_3865,
      IB => UUT_delay_count_share0000_4_CYMUXF2_3866,
      SEL => UUT_delay_count_share0000_4_CYSELG_3856,
      O => UUT_delay_count_share0000_4_CYMUXG2_3867
    );
  UUT_delay_count_share0000_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_4_G,
      O => UUT_delay_count_share0000_4_CYSELG_3856
    );
  UUT_delay_count_share0000_6_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      O => UUT_delay_count_share0000_6_LOGIC_ZERO_3903
    );
  UUT_delay_count_share0000_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_6_XORF_3923,
      O => UUT_delay_count_share0000(6)
    );
  UUT_delay_count_share0000_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      I0 => UUT_delay_count_share0000_6_CYINIT_3922,
      I1 => UUT_delay_count_share0000_6_F,
      O => UUT_delay_count_share0000_6_XORF_3923
    );
  UUT_delay_count_share0000_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      IA => UUT_delay_count_share0000_6_LOGIC_ZERO_3903,
      IB => UUT_delay_count_share0000_6_CYINIT_3922,
      SEL => UUT_delay_count_share0000_6_CYSELF_3909,
      O => UUT_Madd_delay_count_share0000_cy_6_Q
    );
  UUT_delay_count_share0000_6_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      IA => UUT_delay_count_share0000_6_LOGIC_ZERO_3903,
      IB => UUT_delay_count_share0000_6_LOGIC_ZERO_3903,
      SEL => UUT_delay_count_share0000_6_CYSELF_3909,
      O => UUT_delay_count_share0000_6_CYMUXF2_3904
    );
  UUT_delay_count_share0000_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_5_Q,
      O => UUT_delay_count_share0000_6_CYINIT_3922
    );
  UUT_delay_count_share0000_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_6_F,
      O => UUT_delay_count_share0000_6_CYSELF_3909
    );
  UUT_delay_count_share0000_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_6_XORG_3911,
      O => UUT_delay_count_share0000(7)
    );
  UUT_delay_count_share0000_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_6_Q,
      I1 => UUT_delay_count_share0000_6_G,
      O => UUT_delay_count_share0000_6_XORG_3911
    );
  UUT_delay_count_share0000_6_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_6_CYMUXFAST_3908,
      O => UUT_Madd_delay_count_share0000_cy_7_Q
    );
  UUT_delay_count_share0000_6_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_5_Q,
      O => UUT_delay_count_share0000_6_FASTCARRY_3906
    );
  UUT_delay_count_share0000_6_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      I0 => UUT_delay_count_share0000_6_CYSELG_3894,
      I1 => UUT_delay_count_share0000_6_CYSELF_3909,
      O => UUT_delay_count_share0000_6_CYAND_3907
    );
  UUT_delay_count_share0000_6_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      IA => UUT_delay_count_share0000_6_CYMUXG2_3905,
      IB => UUT_delay_count_share0000_6_FASTCARRY_3906,
      SEL => UUT_delay_count_share0000_6_CYAND_3907,
      O => UUT_delay_count_share0000_6_CYMUXFAST_3908
    );
  UUT_delay_count_share0000_6_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y23"
    )
    port map (
      IA => UUT_delay_count_share0000_6_LOGIC_ZERO_3903,
      IB => UUT_delay_count_share0000_6_CYMUXF2_3904,
      SEL => UUT_delay_count_share0000_6_CYSELG_3894,
      O => UUT_delay_count_share0000_6_CYMUXG2_3905
    );
  UUT_delay_count_share0000_6_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_6_G,
      O => UUT_delay_count_share0000_6_CYSELG_3894
    );
  UUT_delay_count_share0000_8_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y24"
    )
    port map (
      O => UUT_delay_count_share0000_8_LOGIC_ZERO_3941
    );
  UUT_delay_count_share0000_8_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_8_XORF_3961,
      O => UUT_delay_count_share0000(8)
    );
  UUT_delay_count_share0000_8_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y24"
    )
    port map (
      I0 => UUT_delay_count_share0000_8_CYINIT_3960,
      I1 => UUT_delay_count_share0000_8_F,
      O => UUT_delay_count_share0000_8_XORF_3961
    );
  UUT_delay_count_share0000_8_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y24"
    )
    port map (
      IA => UUT_delay_count_share0000_8_LOGIC_ZERO_3941,
      IB => UUT_delay_count_share0000_8_CYINIT_3960,
      SEL => UUT_delay_count_share0000_8_CYSELF_3947,
      O => UUT_Madd_delay_count_share0000_cy_8_Q
    );
  UUT_delay_count_share0000_8_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y24"
    )
    port map (
      IA => UUT_delay_count_share0000_8_LOGIC_ZERO_3941,
      IB => UUT_delay_count_share0000_8_LOGIC_ZERO_3941,
      SEL => UUT_delay_count_share0000_8_CYSELF_3947,
      O => UUT_delay_count_share0000_8_CYMUXF2_3942
    );
  UUT_delay_count_share0000_8_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_7_Q,
      O => UUT_delay_count_share0000_8_CYINIT_3960
    );
  UUT_delay_count_share0000_8_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_8_F,
      O => UUT_delay_count_share0000_8_CYSELF_3947
    );
  UUT_delay_count_share0000_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_8_XORG_3949,
      O => UUT_delay_count_share0000(9)
    );
  UUT_delay_count_share0000_8_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y24"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_8_Q,
      I1 => UUT_delay_count_share0000_8_G,
      O => UUT_delay_count_share0000_8_XORG_3949
    );
  UUT_delay_count_share0000_8_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_8_CYMUXFAST_3946,
      O => UUT_Madd_delay_count_share0000_cy_9_Q
    );
  UUT_delay_count_share0000_8_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_7_Q,
      O => UUT_delay_count_share0000_8_FASTCARRY_3944
    );
  UUT_delay_count_share0000_8_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y24"
    )
    port map (
      I0 => UUT_delay_count_share0000_8_CYSELG_3932,
      I1 => UUT_delay_count_share0000_8_CYSELF_3947,
      O => UUT_delay_count_share0000_8_CYAND_3945
    );
  UUT_delay_count_share0000_8_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y24"
    )
    port map (
      IA => UUT_delay_count_share0000_8_CYMUXG2_3943,
      IB => UUT_delay_count_share0000_8_FASTCARRY_3944,
      SEL => UUT_delay_count_share0000_8_CYAND_3945,
      O => UUT_delay_count_share0000_8_CYMUXFAST_3946
    );
  UUT_delay_count_share0000_8_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y24"
    )
    port map (
      IA => UUT_delay_count_share0000_8_LOGIC_ZERO_3941,
      IB => UUT_delay_count_share0000_8_CYMUXF2_3942,
      SEL => UUT_delay_count_share0000_8_CYSELG_3932,
      O => UUT_delay_count_share0000_8_CYMUXG2_3943
    );
  UUT_delay_count_share0000_8_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_8_G,
      O => UUT_delay_count_share0000_8_CYSELG_3932
    );
  UUT_delay_count_share0000_10_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y25"
    )
    port map (
      O => UUT_delay_count_share0000_10_LOGIC_ZERO_3979
    );
  UUT_delay_count_share0000_10_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_10_XORF_3999,
      O => UUT_delay_count_share0000(10)
    );
  UUT_delay_count_share0000_10_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y25"
    )
    port map (
      I0 => UUT_delay_count_share0000_10_CYINIT_3998,
      I1 => UUT_delay_count_share0000_10_F,
      O => UUT_delay_count_share0000_10_XORF_3999
    );
  UUT_delay_count_share0000_10_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y25"
    )
    port map (
      IA => UUT_delay_count_share0000_10_LOGIC_ZERO_3979,
      IB => UUT_delay_count_share0000_10_CYINIT_3998,
      SEL => UUT_delay_count_share0000_10_CYSELF_3985,
      O => UUT_Madd_delay_count_share0000_cy_10_Q
    );
  UUT_delay_count_share0000_10_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y25"
    )
    port map (
      IA => UUT_delay_count_share0000_10_LOGIC_ZERO_3979,
      IB => UUT_delay_count_share0000_10_LOGIC_ZERO_3979,
      SEL => UUT_delay_count_share0000_10_CYSELF_3985,
      O => UUT_delay_count_share0000_10_CYMUXF2_3980
    );
  UUT_delay_count_share0000_10_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_9_Q,
      O => UUT_delay_count_share0000_10_CYINIT_3998
    );
  UUT_delay_count_share0000_10_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_10_F,
      O => UUT_delay_count_share0000_10_CYSELF_3985
    );
  UUT_delay_count_share0000_10_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_10_XORG_3987,
      O => UUT_delay_count_share0000(11)
    );
  UUT_delay_count_share0000_10_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y25"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_10_Q,
      I1 => UUT_delay_count_share0000_10_G,
      O => UUT_delay_count_share0000_10_XORG_3987
    );
  UUT_delay_count_share0000_10_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_10_CYMUXFAST_3984,
      O => UUT_Madd_delay_count_share0000_cy_11_Q
    );
  UUT_delay_count_share0000_10_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_9_Q,
      O => UUT_delay_count_share0000_10_FASTCARRY_3982
    );
  UUT_delay_count_share0000_10_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y25"
    )
    port map (
      I0 => UUT_delay_count_share0000_10_CYSELG_3970,
      I1 => UUT_delay_count_share0000_10_CYSELF_3985,
      O => UUT_delay_count_share0000_10_CYAND_3983
    );
  UUT_delay_count_share0000_10_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y25"
    )
    port map (
      IA => UUT_delay_count_share0000_10_CYMUXG2_3981,
      IB => UUT_delay_count_share0000_10_FASTCARRY_3982,
      SEL => UUT_delay_count_share0000_10_CYAND_3983,
      O => UUT_delay_count_share0000_10_CYMUXFAST_3984
    );
  UUT_delay_count_share0000_10_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y25"
    )
    port map (
      IA => UUT_delay_count_share0000_10_LOGIC_ZERO_3979,
      IB => UUT_delay_count_share0000_10_CYMUXF2_3980,
      SEL => UUT_delay_count_share0000_10_CYSELG_3970,
      O => UUT_delay_count_share0000_10_CYMUXG2_3981
    );
  UUT_delay_count_share0000_10_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_10_G,
      O => UUT_delay_count_share0000_10_CYSELG_3970
    );
  UUT_delay_count_share0000_12_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y26"
    )
    port map (
      O => UUT_delay_count_share0000_12_LOGIC_ZERO_4017
    );
  UUT_delay_count_share0000_12_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_12_XORF_4037,
      O => UUT_delay_count_share0000(12)
    );
  UUT_delay_count_share0000_12_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y26"
    )
    port map (
      I0 => UUT_delay_count_share0000_12_CYINIT_4036,
      I1 => UUT_delay_count_share0000_12_F,
      O => UUT_delay_count_share0000_12_XORF_4037
    );
  UUT_delay_count_share0000_12_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y26"
    )
    port map (
      IA => UUT_delay_count_share0000_12_LOGIC_ZERO_4017,
      IB => UUT_delay_count_share0000_12_CYINIT_4036,
      SEL => UUT_delay_count_share0000_12_CYSELF_4023,
      O => UUT_Madd_delay_count_share0000_cy_12_Q
    );
  UUT_delay_count_share0000_12_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y26"
    )
    port map (
      IA => UUT_delay_count_share0000_12_LOGIC_ZERO_4017,
      IB => UUT_delay_count_share0000_12_LOGIC_ZERO_4017,
      SEL => UUT_delay_count_share0000_12_CYSELF_4023,
      O => UUT_delay_count_share0000_12_CYMUXF2_4018
    );
  UUT_delay_count_share0000_12_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_11_Q,
      O => UUT_delay_count_share0000_12_CYINIT_4036
    );
  UUT_delay_count_share0000_12_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_12_F,
      O => UUT_delay_count_share0000_12_CYSELF_4023
    );
  UUT_delay_count_share0000_12_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_12_XORG_4025,
      O => UUT_delay_count_share0000(13)
    );
  UUT_delay_count_share0000_12_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y26"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_12_Q,
      I1 => UUT_delay_count_share0000_12_G,
      O => UUT_delay_count_share0000_12_XORG_4025
    );
  UUT_delay_count_share0000_12_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_11_Q,
      O => UUT_delay_count_share0000_12_FASTCARRY_4020
    );
  UUT_delay_count_share0000_12_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y26"
    )
    port map (
      I0 => UUT_delay_count_share0000_12_CYSELG_4008,
      I1 => UUT_delay_count_share0000_12_CYSELF_4023,
      O => UUT_delay_count_share0000_12_CYAND_4021
    );
  UUT_delay_count_share0000_12_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y26"
    )
    port map (
      IA => UUT_delay_count_share0000_12_CYMUXG2_4019,
      IB => UUT_delay_count_share0000_12_FASTCARRY_4020,
      SEL => UUT_delay_count_share0000_12_CYAND_4021,
      O => UUT_delay_count_share0000_12_CYMUXFAST_4022
    );
  UUT_delay_count_share0000_12_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y26"
    )
    port map (
      IA => UUT_delay_count_share0000_12_LOGIC_ZERO_4017,
      IB => UUT_delay_count_share0000_12_CYMUXF2_4018,
      SEL => UUT_delay_count_share0000_12_CYSELG_4008,
      O => UUT_delay_count_share0000_12_CYMUXG2_4019
    );
  UUT_delay_count_share0000_12_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_12_G,
      O => UUT_delay_count_share0000_12_CYSELG_4008
    );
  UUT_delay_count_share0000_14_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y27"
    )
    port map (
      O => UUT_delay_count_share0000_14_LOGIC_ZERO_4067
    );
  UUT_delay_count_share0000_14_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_14_XORF_4068,
      O => UUT_delay_count_share0000(14)
    );
  UUT_delay_count_share0000_14_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X21Y27"
    )
    port map (
      I0 => UUT_delay_count_share0000_14_CYINIT_4066,
      I1 => UUT_delay_count_share0000_14_F,
      O => UUT_delay_count_share0000_14_XORF_4068
    );
  UUT_delay_count_share0000_14_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X21Y27"
    )
    port map (
      IA => UUT_delay_count_share0000_14_LOGIC_ZERO_4067,
      IB => UUT_delay_count_share0000_14_CYINIT_4066,
      SEL => UUT_delay_count_share0000_14_CYSELF_4057,
      O => UUT_Madd_delay_count_share0000_cy_14_Q
    );
  UUT_delay_count_share0000_14_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X21Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_12_CYMUXFAST_4022,
      O => UUT_delay_count_share0000_14_CYINIT_4066
    );
  UUT_delay_count_share0000_14_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_14_F,
      O => UUT_delay_count_share0000_14_CYSELF_4057
    );
  UUT_delay_count_share0000_14_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_14_XORG_4054,
      O => UUT_delay_count_share0000(15)
    );
  UUT_delay_count_share0000_14_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X21Y27"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_14_Q,
      I1 => UUT_delay_count_15_rt_4051,
      O => UUT_delay_count_share0000_14_XORG_4054
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X31Y50"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ONE_4084
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X31Y50"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ZERO_4099
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X31Y50"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ZERO_4099,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYINIT_4098,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELF_4089,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_0_Q
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X31Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYINIT_4098
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X31Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut(0),
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELF_4089
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X31Y50"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ONE_4084,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_0_Q,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELG_4076,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYMUXG_4086
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X31Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut(1),
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELG_4076
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X31Y51"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ONE_4114
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X31Y51"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ZERO_4130
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X31Y51"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ZERO_4130,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ZERO_4130,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELF_4120,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXF2_4115
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X31Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut(2),
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELF_4120
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X31Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYMUXG_4086,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_FASTCARRY_4117
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X31Y51"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELG_4107,
      I1 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELF_4120,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYAND_4118
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X31Y51"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXG2_4116,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_3_FASTCARRY_4117,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYAND_4118,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXFAST_4119
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X31Y51"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ONE_4114,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXF2_4115,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELG_4107,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXG2_4116
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X31Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut(3),
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELG_4107
    );
  N91_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X31Y52"
    )
    port map (
      O => N91_LOGIC_ZERO_4157
    );
  N91_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X31Y52"
    )
    port map (
      IA => N91_LOGIC_ZERO_4157,
      IB => N91_CYINIT_4156,
      SEL => N91_CYSELF_4150,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_4_Q
    );
  N91_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X31Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXFAST_4119,
      O => N91_CYINIT_4156
    );
  N91_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X31Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut(4),
      O => N91_CYSELF_4150
    );
  N91_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => N91,
      O => N91_0
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X21Y34"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_LOGIC_ZERO_4557
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y34"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_5_LOGIC_ZERO_4557,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_5_LOGIC_ZERO_4557,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELF_4563,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXF2_4558
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X21Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(4),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELF_4563
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXFAST_4562,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X21Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXFAST_4528,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_FASTCARRY_4560
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X21Y34"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELG_4550,
      I1 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELF_4563,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYAND_4561
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X21Y34"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXG2_4559,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_5_FASTCARRY_4560,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYAND_4561,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXFAST_4562
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X21Y34"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_5_LOGIC_ZERO_4557,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXF2_4558,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELG_4550,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXG2_4559
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X21Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(5),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELG_4550
    );
  I2C_Data_PULLUP : X_PU
    generic map(
      LOC => "PAD18"
    )
    port map (
      O => I2C_Data
    );
  UUT_IOBUF_inst_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD18"
    )
    port map (
      I => I2C_Data_O,
      CTL => I2C_Data_T,
      O => I2C_Data
    );
  UUT_IOBUF_inst_IBUF : X_BUF
    generic map(
      LOC => "PAD18",
      PATHPULSE => 798 ps
    )
    port map (
      I => I2C_Data,
      O => I2C_Data_INBUF
    );
  SW_0_IBUF : X_BUF
    generic map(
      LOC => "PAD124",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW(0),
      O => SW_0_INBUF
    );
  SW_0_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD124",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW_0_INBUF,
      O => SW_0_IBUF_2440
    );
  SW_1_IBUF : X_BUF
    generic map(
      LOC => "PAD117",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW(1),
      O => SW_1_INBUF
    );
  SW_1_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD117",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW_1_INBUF,
      O => SW_1_IBUF_2441
    );
  SW_2_IBUF : X_BUF
    generic map(
      LOC => "PAD116",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW(2),
      O => SW_2_INBUF
    );
  SW_2_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD116",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW_2_INBUF,
      O => SW_2_IBUF_2442
    );
  SW_3_IBUF : X_BUF
    generic map(
      LOC => "IPAD21",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW(3),
      O => SW_3_INBUF
    );
  SW_3_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD21",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW_3_INBUF,
      O => SW_3_IBUF_2443
    );
  FPGA_Clk_BUFGP_IBUFG : X_BUF
    generic map(
      LOC => "IPAD108",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk,
      O => FPGA_Clk_INBUF
    );
  I2C_Clk_PULLUP : X_PU
    generic map(
      LOC => "PAD19"
    )
    port map (
      O => I2C_Clk
    );
  I2C_Clk_OBUF : X_OBUF
    generic map(
      LOC => "PAD19"
    )
    port map (
      I => I2C_Clk_O,
      O => I2C_Clk
    );
  FPGA_Clk_BUFGP_BUFG : X_BUFGMUX
    generic map(
      LOC => "BUFGMUX_X2Y1"
    )
    port map (
      I0 => FPGA_Clk_BUFGP_BUFG_I0_INV,
      I1 => GND,
      S => FPGA_Clk_BUFGP_BUFG_S_INVNOT,
      O => FPGA_Clk_BUFGP
    );
  FPGA_Clk_BUFGP_BUFG_SINV : X_INV
    generic map(
      LOC => "BUFGMUX_X2Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => FPGA_Clk_BUFGP_BUFG_S_INVNOT
    );
  FPGA_Clk_BUFGP_BUFG_I0_USED : X_BUF
    generic map(
      LOC => "BUFGMUX_X2Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_INBUF,
      O => FPGA_Clk_BUFGP_BUFG_I0_INV
    );
  UUT_Mtridata_in_i2c_not000181_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y46",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_not000181_F5MUX_4657,
      O => UUT_Mtridata_in_i2c_not000181
    );
  UUT_Mtridata_in_i2c_not000181_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X27Y46"
    )
    port map (
      IA => N189,
      IB => N190,
      SEL => UUT_Mtridata_in_i2c_not000181_BXINV_4650,
      O => UUT_Mtridata_in_i2c_not000181_F5MUX_4657
    );
  UUT_Mtridata_in_i2c_not000181_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y46",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count(5),
      O => UUT_Mtridata_in_i2c_not000181_BXINV_4650
    );
  UUT_writeCount_0_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X29Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_0_F5MUX_4684,
      O => UUT_writeCount_0_DXMUX_4686
    );
  UUT_writeCount_0_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X29Y16"
    )
    port map (
      IA => N197,
      IB => N198,
      SEL => UUT_writeCount_0_BXINV_4677,
      O => UUT_writeCount_0_F5MUX_4684
    );
  UUT_writeCount_0_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X29Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N32_0,
      O => UUT_writeCount_0_BXINV_4677
    );
  UUT_writeCount_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X29Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_0_CLKINV_4669
    );
  UUT_writeCount_mux0000_0_F : X_LUT4
    generic map(
      INIT => X"8A8A",
      LOC => "SLICE_X29Y16"
    )
    port map (
      ADR0 => UUT_writeCount(0),
      ADR1 => UUT_nstate_FFd1_2447,
      ADR2 => UUT_nstate_FFd3_2450,
      ADR3 => VCC,
      O => N197
    );
  UUT_nstate_FFd2_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd2_FXMUX_4719,
      O => UUT_nstate_FFd2_DXMUX_4720
    );
  UUT_nstate_FFd2_FXMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd2_F5MUX_4718,
      O => UUT_nstate_FFd2_FXMUX_4719
    );
  UUT_nstate_FFd2_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X25Y39"
    )
    port map (
      IA => N142,
      IB => N143,
      SEL => UUT_nstate_FFd2_BXINV_4711,
      O => UUT_nstate_FFd2_F5MUX_4718
    );
  UUT_nstate_FFd2_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd3_2450,
      O => UUT_nstate_FFd2_BXINV_4711
    );
  UUT_nstate_FFd2_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N65_0,
      O => UUT_nstate_FFd2_SRINV_4703
    );
  UUT_nstate_FFd2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_nstate_FFd2_CLKINV_4702
    );
  UUT_nstate_FFd2_In1_F : X_LUT4
    generic map(
      INIT => X"AA22",
      LOC => "SLICE_X25Y39"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => UUT_nstate_FFd1_2447,
      ADR2 => VCC,
      ADR3 => UUT_nstate_FFd4_2454,
      O => N142
    );
  UUT_nstate_FFd1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd1_FXMUX_4754,
      O => UUT_nstate_FFd1_DXMUX_4755
    );
  UUT_nstate_FFd1_FXMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd1_F5MUX_4753,
      O => UUT_nstate_FFd1_FXMUX_4754
    );
  UUT_nstate_FFd1_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X27Y40"
    )
    port map (
      IA => N199,
      IB => N200,
      SEL => UUT_nstate_FFd1_BXINV_4746,
      O => UUT_nstate_FFd1_F5MUX_4753
    );
  UUT_nstate_FFd1_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd3_2450,
      O => UUT_nstate_FFd1_BXINV_4746
    );
  UUT_nstate_FFd1_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N65_0,
      O => UUT_nstate_FFd1_SRINV_4738
    );
  UUT_nstate_FFd1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_nstate_FFd1_CLKINV_4737
    );
  UUT_nstate_FFd1_In271_F : X_LUT4
    generic map(
      INIT => X"C000",
      LOC => "SLICE_X27Y40"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_nstate_FFd4_2454,
      ADR2 => UUT_nstate_cmp_eq0001_0,
      ADR3 => UUT_nstate_FFd2_2446,
      O => N199
    );
  UUT_counter_mux0000_0_F : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X26Y34"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0010,
      ADR1 => UUT_Madd_counter_addsub0000_cy_2_0,
      ADR2 => UUT_ClkRisingEdge_2465,
      ADR3 => UUT_counter(3),
      O => N191
    );
  UUT_counter_4_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X26Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_4_F5MUX_4785,
      O => UUT_counter_4_DXMUX_4787
    );
  UUT_counter_4_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X26Y34"
    )
    port map (
      IA => N191,
      IB => N192,
      SEL => UUT_counter_4_BXINV_4778,
      O => UUT_counter_4_F5MUX_4785
    );
  UUT_counter_4_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter(4),
      O => UUT_counter_4_BXINV_4778
    );
  UUT_counter_4_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_counter_4_CLKINV_4771
    );
  UUT_counter_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_3_F5MUX_4816,
      O => UUT_counter_3_DXMUX_4818
    );
  UUT_counter_3_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X27Y35"
    )
    port map (
      IA => N185,
      IB => N186,
      SEL => UUT_counter_3_BXINV_4809,
      O => UUT_counter_3_F5MUX_4816
    );
  UUT_counter_3_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_counter_addsub0000_cy_2_0,
      O => UUT_counter_3_BXINV_4809
    );
  UUT_counter_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_counter_3_CLKINV_4801
    );
  UUT_counter_mux0000_1_F : X_LUT4
    generic map(
      INIT => X"E0E0",
      LOC => "SLICE_X27Y35"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => UUT_N112_0,
      ADR2 => UUT_counter(3),
      ADR3 => VCC,
      O => N185
    );
  UUT_counter_2_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_2_F5MUX_4847,
      O => UUT_counter_2_DXMUX_4849
    );
  UUT_counter_2_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X25Y34"
    )
    port map (
      IA => N193,
      IB => N194,
      SEL => UUT_counter_2_BXINV_4840,
      O => UUT_counter_2_F5MUX_4847
    );
  UUT_counter_2_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter(2),
      O => UUT_counter_2_BXINV_4840
    );
  UUT_counter_2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_counter_2_CLKINV_4833
    );
  UUT_counter_mux0000_2_F : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X25Y34"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2465,
      ADR1 => UUT_nstate_cmp_eq0010,
      ADR2 => UUT_counter(0),
      ADR3 => UUT_counter(1),
      O => N193
    );
  UUT_counter_1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_1_F5MUX_4878,
      O => UUT_counter_1_DXMUX_4880
    );
  UUT_counter_1_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X25Y35"
    )
    port map (
      IA => N187,
      IB => N188,
      SEL => UUT_counter_1_BXINV_4870,
      O => UUT_counter_1_F5MUX_4878
    );
  UUT_counter_1_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter(1),
      O => UUT_counter_1_BXINV_4870
    );
  UUT_counter_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_counter_1_CLKINV_4862
    );
  UUT_counter_mux0000_3_F : X_LUT4
    generic map(
      INIT => X"8080",
      LOC => "SLICE_X25Y35"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2465,
      ADR1 => UUT_nstate_cmp_eq0010,
      ADR2 => UUT_counter(0),
      ADR3 => VCC,
      O => N187
    );
  UUT_nstate_FFd4_In37_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y42",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_In37_F5MUX_4907,
      O => UUT_nstate_FFd4_In37
    );
  UUT_nstate_FFd4_In37_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X24Y42"
    )
    port map (
      IA => N195,
      IB => N196,
      SEL => UUT_nstate_FFd4_In37_BXINV_4900,
      O => UUT_nstate_FFd4_In37_F5MUX_4907
    );
  UUT_nstate_FFd4_In37_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y42",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd3_2450,
      O => UUT_nstate_FFd4_In37_BXINV_4900
    );
  N103_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => N103_F5MUX_4932,
      O => N103
    );
  N103_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X24Y30"
    )
    port map (
      IA => N138,
      IB => N139,
      SEL => N103_BXINV_4925,
      O => N103_F5MUX_4932
    );
  N103_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_240_2471,
      O => N103_BXINV_4925
    );
  N106_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => N106_F5MUX_4957,
      O => N106
    );
  N106_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X25Y33"
    )
    port map (
      IA => N140,
      IB => N141,
      SEL => N106_BXINV_4950,
      O => N106_F5MUX_4957
    );
  N106_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_240_2471,
      O => N106_BXINV_4950
    );
  N33_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => N33,
      O => N33_0
    );
  N33_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_mux0000231_O_pack_1,
      O => UUT_Mtridata_in_i2c_mux0000231_O
    );
  UUT_Mtridata_in_i2c_mux0000231 : X_LUT4
    generic map(
      INIT => X"A0A0",
      LOC => "SLICE_X23Y33"
    )
    port map (
      ADR0 => UUT_shiftReg_cmp_eq0002_0,
      ADR1 => VCC,
      ADR2 => UUT_shiftReg_and0000_0,
      ADR3 => VCC,
      O => UUT_Mtridata_in_i2c_mux0000231_O_pack_1
    );
  UUT_Dir_mux000011_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y46",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux000011_5004,
      O => UUT_Dir_mux000011_0
    );
  UUT_Dir_mux000011_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y46",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux000011_SW0_O_pack_1,
      O => UUT_Dir_mux000011_SW0_O
    );
  UUT_Dir_mux000011_SW0 : X_LUT4
    generic map(
      INIT => X"FFFD",
      LOC => "SLICE_X28Y46"
    )
    port map (
      ADR0 => UUT_ack_count(5),
      ADR1 => UUT_ack_count(0),
      ADR2 => UUT_ack_count(2),
      ADR3 => UUT_ack_count(1),
      O => UUT_Dir_mux000011_SW0_O_pack_1
    );
  UUT_Mtridata_in_i2c_mux000094_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_mux000094_5028,
      O => UUT_Mtridata_in_i2c_mux000094_0
    );
  UUT_Mtridata_in_i2c_mux000094_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_mux000091_O_pack_1,
      O => UUT_Mtridata_in_i2c_mux000091_O
    );
  UUT_Mtridata_in_i2c_mux000091 : X_LUT4
    generic map(
      INIT => X"0202",
      LOC => "SLICE_X23Y37"
    )
    port map (
      ADR0 => UUT_N45,
      ADR1 => UUT_delay_count(0),
      ADR2 => UUT_delay_count(1),
      ADR3 => VCC,
      O => UUT_Mtridata_in_i2c_mux000091_O_pack_1
    );
  UUT_pstate_mux0000_5_115_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000_5_115_5052,
      O => UUT_pstate_mux0000_5_115_0
    );
  UUT_pstate_mux0000_5_115_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000_5_115_SW0_O_pack_1,
      O => UUT_pstate_mux0000_5_115_SW0_O
    );
  UUT_pstate_mux0000_5_115_SW0 : X_LUT4
    generic map(
      INIT => X"8080",
      LOC => "SLICE_X26Y43"
    )
    port map (
      ADR0 => N35_0,
      ADR1 => UUT_ack_count(0),
      ADR2 => UUT_ack_count(5),
      ADR3 => VCC,
      O => UUT_pstate_mux0000_5_115_SW0_O_pack_1
    );
  N98_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y42",
      PATHPULSE => 798 ps
    )
    port map (
      I => N98,
      O => N98_0
    );
  N98_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y42",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000_5_1129_pack_1,
      O => UUT_pstate_mux0000_5_1129_2498
    );
  UUT_pstate_mux0000_5_1129 : X_LUT4
    generic map(
      INIT => X"7272",
      LOC => "SLICE_X27Y42"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => UUT_nstate_cmp_eq0001_0,
      ADR2 => UUT_Mcompar_nstate_cmp_gt0000_cy_4_Q,
      ADR3 => VCC,
      O => UUT_pstate_mux0000_5_1129_pack_1
    );
  UUT_N50_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N50,
      O => UUT_N50_0
    );
  UUT_N50_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_cmp_eq00001_SW0_O_pack_1,
      O => UUT_Mtridata_in_i2c_cmp_eq00001_SW0_O
    );
  UUT_Mtridata_in_i2c_cmp_eq00001_SW0 : X_LUT4
    generic map(
      INIT => X"FFEE",
      LOC => "SLICE_X26Y51"
    )
    port map (
      ADR0 => UUT_ack_count(5),
      ADR1 => UUT_ack_count(0),
      ADR2 => VCC,
      ADR3 => UUT_ack_count(4),
      O => UUT_Mtridata_in_i2c_cmp_eq00001_SW0_O_pack_1
    );
  UUT_pstate_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000(5),
      O => UUT_pstate_3_DXMUX_5129
    );
  UUT_pstate_3_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000_5_1178_SW1_SW0_O_pack_1,
      O => UUT_pstate_mux0000_5_1178_SW1_SW0_O
    );
  UUT_pstate_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_pstate_3_CLKINV_5114
    );
  UUT_pstate_mux0000_5_1178_SW1_SW0 : X_LUT4
    generic map(
      INIT => X"FFEA",
      LOC => "SLICE_X24Y43"
    )
    port map (
      ADR0 => N43_0,
      ADR1 => UUT_pstate_mux0000_5_1129_2498,
      ADR2 => UUT_N69_0,
      ADR3 => N56_0,
      O => UUT_pstate_mux0000_5_1178_SW1_SW0_O_pack_1
    );
  UUT_Mtridata_in_i2c_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_mux0000,
      O => UUT_Mtridata_in_i2c_DXMUX_5161
    );
  UUT_Mtridata_in_i2c_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_mux000034_O_pack_1,
      O => UUT_Mtridata_in_i2c_mux000034_O
    );
  UUT_Mtridata_in_i2c_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_Mtridata_in_i2c_CLKINV_5146
    );
  UUT_Mtridata_in_i2c_CEINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_not0001_0,
      O => UUT_Mtridata_in_i2c_CEINV_5145
    );
  UUT_Mtridata_in_i2c_mux000034 : X_LUT4
    generic map(
      INIT => X"A0EC",
      LOC => "SLICE_X27Y41"
    )
    port map (
      ADR0 => UUT_Mtridata_in_i2c_cmp_eq0000,
      ADR1 => UUT_N50_0,
      ADR2 => UUT_nstate_cmp_eq0006_0,
      ADR3 => N128_0,
      O => UUT_Mtridata_in_i2c_mux000034_O_pack_1
    );
  UUT_N3_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N3,
      O => UUT_N3_0
    );
  UUT_N3_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N362_pack_1,
      O => UUT_N362_2519
    );
  UUT_N362 : X_LUT4
    generic map(
      INIT => X"FB00",
      LOC => "SLICE_X28Y50"
    )
    port map (
      ADR0 => UUT_ack_count(1),
      ADR1 => UUT_N50_0,
      ADR2 => UUT_ack_count(6),
      ADR3 => UUT_nstate_cmp_eq0006_0,
      O => UUT_N362_pack_1
    );
  UUT_Dir_mux0000121_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000121_5211,
      O => UUT_Dir_mux0000121_0
    );
  UUT_Dir_mux0000121_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000108_O_pack_1,
      O => UUT_Dir_mux0000108_O
    );
  UUT_Dir_mux0000108 : X_LUT4
    generic map(
      INIT => X"0C5D",
      LOC => "SLICE_X24Y44"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2454,
      ADR1 => UUT_ack_count(1),
      ADR2 => UUT_nstate_FFd2_2446,
      ADR3 => UUT_nstate_FFd1_2447,
      O => UUT_Dir_mux0000108_O_pack_1
    );
  UUT_N3157_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N3157_5235,
      O => UUT_N3157_0
    );
  UUT_N3157_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N3157_SW0_O_pack_1,
      O => UUT_N3157_SW0_O
    );
  UUT_N3157_SW0 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X29Y57"
    )
    port map (
      ADR0 => UUT_ack_count(1),
      ADR1 => UUT_ack_count(0),
      ADR2 => UUT_ack_count(3),
      ADR3 => UUT_ack_count(2),
      O => UUT_N3157_SW0_O_pack_1
    );
  UUT_N3178_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N3178_5259,
      O => UUT_N3178_0
    );
  UUT_N3178_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N3106_O_pack_1,
      O => UUT_N3106_O
    );
  UUT_N3106 : X_LUT4
    generic map(
      INIT => X"B0BB",
      LOC => "SLICE_X29Y56"
    )
    port map (
      ADR0 => UUT_ack_count(4),
      ADR1 => N119_0,
      ADR2 => UUT_ack_count(5),
      ADR3 => UUT_ack_count(8),
      O => UUT_N3106_O_pack_1
    );
  UUT_Dir_mux000061_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y47",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000611_SW0_O_pack_1,
      O => UUT_Dir_mux0000611_SW0_O
    );
  UUT_Dir_mux0000611_SW0 : X_LUT4
    generic map(
      INIT => X"8100",
      LOC => "SLICE_X29Y47"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => UUT_ack_count(8),
      ADR2 => UUT_ack_count(0),
      ADR3 => UUT_N69_0,
      O => UUT_Dir_mux0000611_SW0_O_pack_1
    );
  N51_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => N51,
      O => N51_0
    );
  N51_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtrien_in_i2c_mux00002_SW0_SW0_O_pack_1,
      O => UUT_Mtrien_in_i2c_mux00002_SW0_SW0_O
    );
  UUT_Mtrien_in_i2c_mux00002_SW0_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X20Y28"
    )
    port map (
      ADR0 => UUT_delay_count(7),
      ADR1 => UUT_delay_count(1),
      ADR2 => UUT_delay_count(0),
      ADR3 => UUT_delay_count(9),
      O => UUT_Mtrien_in_i2c_mux00002_SW0_SW0_O_pack_1
    );
  UUT_shiftReg_and0000_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_and0000,
      O => UUT_shiftReg_and0000_0
    );
  UUT_shiftReg_and0000_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq00031_SW1_O_pack_1,
      O => UUT_shiftReg_cmp_eq00031_SW1_O
    );
  UUT_shiftReg_cmp_eq00031_SW1 : X_LUT4
    generic map(
      INIT => X"FFFA",
      LOC => "SLICE_X21Y30"
    )
    port map (
      ADR0 => UUT_delay_count(15),
      ADR1 => VCC,
      ADR2 => UUT_delay_count(2),
      ADR3 => UUT_delay_count(3),
      O => UUT_shiftReg_cmp_eq00031_SW1_O_pack_1
    );
  UUT_nstate_FFd3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd3_FXMUX_5360,
      O => UUT_nstate_FFd3_DXMUX_5361
    );
  UUT_nstate_FFd3_FXMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd3_In_5358,
      O => UUT_nstate_FFd3_FXMUX_5360
    );
  UUT_nstate_FFd3_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd3_In_SW0_O_pack_1,
      O => UUT_nstate_FFd3_In_SW0_O
    );
  UUT_nstate_FFd3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_nstate_FFd3_CLKINV_5345
    );
  UUT_nstate_FFd3_In_SW0 : X_LUT4
    generic map(
      INIT => X"0202",
      LOC => "SLICE_X27Y43"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2454,
      ADR1 => UUT_nstate_FFd2_2446,
      ADR2 => UUT_Mcompar_nstate_cmp_gt0000_cy_4_Q,
      ADR3 => VCC,
      O => UUT_nstate_FFd3_In_SW0_O_pack_1
    );
  UUT_N31_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N31,
      O => UUT_N31_0
    );
  UUT_N31_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_or0000_pack_1,
      O => UUT_shiftReg_or0000
    );
  UUT_N14_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N14,
      O => UUT_N14_0
    );
  UUT_N14_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000_10_25_SW0_O_pack_1,
      O => UUT_ack_count_mux0000_10_25_SW0_O
    );
  UUT_ack_count_mux0000_10_25_SW0 : X_LUT4
    generic map(
      INIT => X"EFFF",
      LOC => "SLICE_X30Y51"
    )
    port map (
      ADR0 => UUT_ack_count(1),
      ADR1 => UUT_ack_count(6),
      ADR2 => UUT_N50_0,
      ADR3 => UUT_nstate_cmp_eq0006_0,
      O => UUT_ack_count_mux0000_10_25_SW0_O_pack_1
    );
  UUT_N320_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N320_5968,
      O => UUT_N320_0
    );
  UUT_N320_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N33_O_pack_1,
      O => UUT_N33_O
    );
  UUT_N33 : X_LUT4
    generic map(
      INIT => X"3F3F",
      LOC => "SLICE_X30Y48"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(3),
      ADR2 => UUT_ack_count(0),
      ADR3 => VCC,
      O => UUT_N33_O_pack_1
    );
  UUT_N349_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N349_5992,
      O => UUT_N349_0
    );
  UUT_N349_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_and0025_pack_1,
      O => UUT_ack_count_and0025
    );
  UUT_out_i2cclk_mux000081 : X_LUT4
    generic map(
      INIT => X"1010",
      LOC => "SLICE_X28Y49"
    )
    port map (
      ADR0 => UUT_N41,
      ADR1 => UUT_ack_count(1),
      ADR2 => UUT_N53_0,
      ADR3 => VCC,
      O => UUT_ack_count_and0025_pack_1
    );
  UUT_N62_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N62,
      O => UUT_N62_0
    );
  UUT_N62_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0010_pack_1,
      O => UUT_nstate_cmp_eq0010
    );
  UUT_counter_mux0000_0_21 : X_LUT4
    generic map(
      INIT => X"0010",
      LOC => "SLICE_X24Y39"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_1_2598,
      ADR1 => UUT_nstate_FFd1_1_2596,
      ADR2 => UUT_nstate_FFd2_1_2599,
      ADR3 => UUT_nstate_FFd4_1_2597,
      O => UUT_nstate_cmp_eq0010_pack_1
    );
  UUT_N392_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N392_6040,
      O => UUT_N392_0
    );
  UUT_N392_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N392_SW0_O_pack_1,
      O => UUT_N392_SW0_O
    );
  UUT_N392_SW0 : X_LUT4
    generic map(
      INIT => X"0FCE",
      LOC => "SLICE_X30Y56"
    )
    port map (
      ADR0 => UUT_ack_count(5),
      ADR1 => UUT_ack_count(7),
      ADR2 => UUT_ack_count(8),
      ADR3 => UUT_ack_count(6),
      O => UUT_N392_SW0_O_pack_1
    );
  UUT_shiftReg_or000017_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_or000017_6064,
      O => UUT_shiftReg_or000017_0
    );
  UUT_shiftReg_or000017_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_or000012_O_pack_1,
      O => UUT_shiftReg_or000012_O
    );
  UUT_shiftReg_or000012 : X_LUT4
    generic map(
      INIT => X"0FFF",
      LOC => "SLICE_X18Y27"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(0),
      ADR3 => UUT_delay_count(6),
      O => UUT_shiftReg_or000012_O_pack_1
    );
  UUT_shiftReg_mux0000_0_110_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_110_6088,
      O => UUT_shiftReg_mux0000_0_110_0
    );
  UUT_shiftReg_mux0000_0_110_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_131_O_pack_1,
      O => UUT_shiftReg_mux0000_0_131_O
    );
  UUT_shiftReg_mux0000_0_131 : X_LUT4
    generic map(
      INIT => X"3030",
      LOC => "SLICE_X24Y31"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ClkRisingEdge_2465,
      ADR2 => UUT_nstate_cmp_eq0010,
      ADR3 => VCC,
      O => UUT_shiftReg_mux0000_0_131_O_pack_1
    );
  UUT_N13_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N13,
      O => UUT_N13_0
    );
  UUT_N13_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N45_pack_1,
      O => UUT_N45
    );
  UUT_shiftReg_cmp_eq00032 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X22Y28"
    )
    port map (
      ADR0 => UUT_delay_count(7),
      ADR1 => UUT_delay_count(4),
      ADR2 => N49,
      ADR3 => UUT_delay_count(9),
      O => UUT_N45_pack_1
    );
  UUT_N0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N0,
      O => UUT_N0_0
    );
  UUT_N0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_119_SW1_O_pack_1,
      O => UUT_shiftReg_mux0000_0_119_SW1_O
    );
  UUT_shiftReg_mux0000_0_119_SW1 : X_LUT4
    generic map(
      INIT => X"3222",
      LOC => "SLICE_X24Y28"
    )
    port map (
      ADR0 => UUT_N26_0,
      ADR1 => UUT_ClkFallingEdge_2566,
      ADR2 => UUT_shiftReg_mux0000_0_114_0,
      ADR3 => UUT_N13_0,
      O => UUT_shiftReg_mux0000_0_119_SW1_O_pack_1
    );
  UUT_shiftReg_mux0000_0_216_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_216_6160,
      O => UUT_shiftReg_mux0000_0_216_0
    );
  UUT_shiftReg_mux0000_0_216_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N33_pack_1,
      O => UUT_N33_2487
    );
  UUT_shiftReg_mux0000_0_221 : X_LUT4
    generic map(
      INIT => X"FF80",
      LOC => "SLICE_X23Y31"
    )
    port map (
      ADR0 => N58_0,
      ADR1 => UUT_shiftReg_cmp_eq0001,
      ADR2 => UUT_N38_0,
      ADR3 => UUT_ClkFallingEdge_2566,
      O => UUT_N33_pack_1
    );
  UUT_Mtrien_in_i2c_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X26Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtrien_in_i2c_mux0000,
      O => UUT_Mtrien_in_i2c_DXMUX_6191
    );
  UUT_Mtrien_in_i2c_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtrien_in_i2c_mux00009_O_pack_1,
      O => UUT_Mtrien_in_i2c_mux00009_O
    );
  UUT_Mtrien_in_i2c_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_Mtrien_in_i2c_CLKINV_6176
    );
  UUT_Mtrien_in_i2c_CEINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_not0001_0,
      O => UUT_Mtrien_in_i2c_CEINV_6175
    );
  UUT_Mtrien_in_i2c_mux0000133_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y47",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtrien_in_i2c_mux0000133_6217,
      O => UUT_Mtrien_in_i2c_mux0000133_0
    );
  UUT_Mtrien_in_i2c_mux0000133_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y47",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtrien_in_i2c_mux0000113_O_pack_1,
      O => UUT_Mtrien_in_i2c_mux0000113_O
    );
  UUT_Mtrien_in_i2c_mux0000113 : X_LUT4
    generic map(
      INIT => X"7F7F",
      LOC => "SLICE_X28Y47"
    )
    port map (
      ADR0 => UUT_N57,
      ADR1 => UUT_ack_count(4),
      ADR2 => UUT_ack_count(5),
      ADR3 => VCC,
      O => UUT_Mtrien_in_i2c_mux0000113_O_pack_1
    );
  UUT_out_i2cclk_mux0000104_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux000053_O_pack_1,
      O => UUT_out_i2cclk_mux000053_O
    );
  UUT_out_i2cclk_mux000053 : X_LUT4
    generic map(
      INIT => X"FFF8",
      LOC => "SLICE_X29Y50"
    )
    port map (
      ADR0 => UUT_out_i2cclk_mux000047_0,
      ADR1 => UUT_ack_count_and0025,
      ADR2 => UUT_out_i2cclk_mux00002_0,
      ADR3 => UUT_out_i2cclk_mux000026_0,
      O => UUT_out_i2cclk_mux000053_O_pack_1
    );
  UUT_Mtridata_in_i2c_not0001_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_not0001,
      O => UUT_Mtridata_in_i2c_not0001_0
    );
  UUT_Mtridata_in_i2c_not0001_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_not0001125_O_pack_1,
      O => UUT_Mtridata_in_i2c_not0001125_O
    );
  UUT_Mtridata_in_i2c_not0001125 : X_LUT4
    generic map(
      INIT => X"080A",
      LOC => "SLICE_X27Y49"
    )
    port map (
      ADR0 => UUT_N53_0,
      ADR1 => UUT_Mtridata_in_i2c_not000141_0,
      ADR2 => UUT_ack_count(0),
      ADR3 => N157_0,
      O => UUT_Mtridata_in_i2c_not0001125_O_pack_1
    );
  UUT_out_i2cclk_mux0000176_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000176_6289,
      O => UUT_out_i2cclk_mux0000176_0
    );
  UUT_out_i2cclk_mux0000176_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000163_O_pack_1,
      O => UUT_out_i2cclk_mux0000163_O
    );
  UUT_out_i2cclk_mux0000163 : X_LUT4
    generic map(
      INIT => X"DDFC",
      LOC => "SLICE_X29Y55"
    )
    port map (
      ADR0 => UUT_ack_count(3),
      ADR1 => UUT_out_i2cclk_mux0000162_0,
      ADR2 => UUT_ack_count(7),
      ADR3 => UUT_ack_count(6),
      O => UUT_out_i2cclk_mux0000163_O_pack_1
    );
  UUT_Mtridata_in_i2c_not0001168_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_not0001168_6313,
      O => UUT_Mtridata_in_i2c_not0001168_0
    );
  UUT_Mtridata_in_i2c_not0001168_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_not0001168_SW0_O_pack_1,
      O => UUT_Mtridata_in_i2c_not0001168_SW0_O
    );
  UUT_Mtridata_in_i2c_not0001168_SW0 : X_LUT4
    generic map(
      INIT => X"BFFE",
      LOC => "SLICE_X29Y48"
    )
    port map (
      ADR0 => UUT_nstate_FFd1_2447,
      ADR1 => UUT_ack_count(8),
      ADR2 => UUT_ack_count(0),
      ADR3 => UUT_nstate_FFd2_2446,
      O => UUT_Mtridata_in_i2c_not0001168_SW0_O_pack_1
    );
  N25_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => N25,
      O => N25_0
    );
  N25_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_or0000_pack_1,
      O => UUT_delay_count_or0000
    );
  UUT_delay_count_or00001 : X_LUT4
    generic map(
      INIT => X"F3F3",
      LOC => "SLICE_X28Y16"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_nstate_FFd3_2450,
      ADR2 => UUT_nstate_FFd1_2447,
      ADR3 => VCC,
      O => UUT_delay_count_or0000_pack_1
    );
  UUT_nstate_cmp_eq0000_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0000_6361,
      O => UUT_nstate_cmp_eq0000_0
    );
  UUT_nstate_cmp_eq0000_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0000_SW0_O_pack_1,
      O => UUT_nstate_cmp_eq0000_SW0_O
    );
  UUT_nstate_cmp_eq0000_SW0 : X_LUT4
    generic map(
      INIT => X"DDDD",
      LOC => "SLICE_X27Y34"
    )
    port map (
      ADR0 => UUT_counter(3),
      ADR1 => UUT_counter(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_nstate_cmp_eq0000_SW0_O_pack_1
    );
  UUT_nstate_cmp_eq0001_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0001_6385,
      O => UUT_nstate_cmp_eq0001_0
    );
  UUT_nstate_cmp_eq0001_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N60_pack_1,
      O => UUT_N60
    );
  UUT_Dir_mux0000421 : X_LUT4
    generic map(
      INIT => X"2000",
      LOC => "SLICE_X31Y53"
    )
    port map (
      ADR0 => UUT_ack_count(2),
      ADR1 => UUT_ack_count(5),
      ADR2 => UUT_ack_count(7),
      ADR3 => UUT_ack_count(1),
      O => UUT_N60_pack_1
    );
  UUT_shiftReg_6_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_6_18,
      O => UUT_shiftReg_6_DXMUX_6416
    );
  UUT_shiftReg_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N12_pack_1,
      O => UUT_N12
    );
  UUT_shiftReg_6_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_6_5_6556,
      O => UUT_shiftReg_6_SRINV_6401
    );
  UUT_shiftReg_6_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_6_CLKINV_6400
    );
  UUT_shiftReg_mux0000_0_244 : X_LUT4
    generic map(
      INIT => X"FEAA",
      LOC => "SLICE_X24Y33"
    )
    port map (
      ADR0 => UUT_shiftReg_mux0000_0_240_2471,
      ADR1 => UUT_shiftReg_mux0000_0_216_0,
      ADR2 => UUT_shiftReg_mux0000_0_25_0,
      ADR3 => UUT_N26_0,
      O => UUT_N12_pack_1
    );
  UUT_shiftReg_1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_1_1_6446,
      O => UUT_shiftReg_1_DXMUX_6449
    );
  UUT_shiftReg_1_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_1_SW0_O_pack_1,
      O => UUT_shiftReg_mux0000_1_SW0_O
    );
  UUT_shiftReg_1_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0005_0,
      O => UUT_shiftReg_1_SRINV_6433
    );
  UUT_shiftReg_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_1_CLKINV_6432
    );
  UUT_shiftReg_mux0000_0_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_5_O_pack_1,
      O => UUT_shiftReg_mux0000_0_5_O
    );
  UUT_shiftReg_or000047 : X_LUT4
    generic map(
      INIT => X"FFF8",
      LOC => "SLICE_X20Y29"
    )
    port map (
      ADR0 => UUT_delay_count(10),
      ADR1 => UUT_shiftReg_or000017_0,
      ADR2 => UUT_N331_0,
      ADR3 => UUT_shiftReg_or000032_0,
      O => UUT_shiftReg_or0000_pack_1
    );
  UUT_ack_count_mux0000_0_28_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000_0_18_O_pack_1,
      O => UUT_ack_count_mux0000_0_18_O
    );
  UUT_ack_count_mux0000_0_18 : X_LUT4
    generic map(
      INIT => X"0020",
      LOC => "SLICE_X27Y51"
    )
    port map (
      ADR0 => UUT_N53_0,
      ADR1 => UUT_ack_count(1),
      ADR2 => UUT_ack_count_cmp_eq0003,
      ADR3 => UUT_N41,
      O => UUT_ack_count_mux0000_0_18_O_pack_1
    );
  UUT_N211_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N211,
      O => UUT_N211_0
    );
  UUT_N211_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_cmp_eq0000_pack_1,
      O => UUT_Mtridata_in_i2c_cmp_eq0000
    );
  UUT_Mtridata_in_i2c_cmp_eq00002 : X_LUT4
    generic map(
      INIT => X"000C",
      LOC => "SLICE_X28Y52"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_N50_0,
      ADR2 => UUT_ack_count(1),
      ADR3 => UUT_ack_count(6),
      O => UUT_Mtridata_in_i2c_cmp_eq0000_pack_1
    );
  UUT_N331_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N331,
      O => UUT_N331_0
    );
  UUT_N331_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_or00002_SW0_O_pack_1,
      O => UUT_shiftReg_or00002_SW0_O
    );
  UUT_shiftReg_or00002_SW0 : X_LUT4
    generic map(
      INIT => X"1111",
      LOC => "SLICE_X21Y28"
    )
    port map (
      ADR0 => UUT_delay_count(4),
      ADR1 => UUT_delay_count(6),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_shiftReg_or00002_SW0_O_pack_1
    );
  UUT_out_i2cclk_mux000026_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux000026_5482,
      O => UUT_out_i2cclk_mux000026_0
    );
  UUT_out_i2cclk_mux000026_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux000026_SW0_O_pack_1,
      O => UUT_out_i2cclk_mux000026_SW0_O
    );
  UUT_out_i2cclk_mux000026_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X30Y52"
    )
    port map (
      ADR0 => UUT_ack_count(8),
      ADR1 => UUT_ack_count(11),
      ADR2 => UUT_ack_count(10),
      ADR3 => UUT_ack_count(0),
      O => UUT_out_i2cclk_mux000026_SW0_O_pack_1
    );
  UUT_Mtridata_in_i2c_not000141_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_not000141_5506,
      O => UUT_Mtridata_in_i2c_not000141_0
    );
  UUT_Mtridata_in_i2c_not000141_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_not000111_O_pack_1,
      O => UUT_Mtridata_in_i2c_not000111_O
    );
  UUT_Mtridata_in_i2c_not000111 : X_LUT4
    generic map(
      INIT => X"B888",
      LOC => "SLICE_X27Y48"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2450,
      ADR1 => UUT_nstate_FFd4_2454,
      ADR2 => UUT_nstate_FFd1_2447,
      ADR3 => UUT_nstate_FFd2_2446,
      O => UUT_Mtridata_in_i2c_not000111_O_pack_1
    );
  UUT_out_i2cclk_mux000047_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux000047_5530,
      O => UUT_out_i2cclk_mux000047_0
    );
  UUT_out_i2cclk_mux000047_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N57_pack_1,
      O => UUT_N57
    );
  UUT_Mtridata_in_i2c_cmp_eq000111 : X_LUT4
    generic map(
      INIT => X"0101",
      LOC => "SLICE_X31Y48"
    )
    port map (
      ADR0 => UUT_ack_count(6),
      ADR1 => UUT_ack_count(0),
      ADR2 => UUT_ack_count(3),
      ADR3 => VCC,
      O => UUT_N57_pack_1
    );
  UUT_out_i2cclk_mux000066_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux000066_5554,
      O => UUT_out_i2cclk_mux000066_0
    );
  UUT_out_i2cclk_mux000066_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N27_pack_1,
      O => UUT_N27
    );
  UUT_Dir_mux00002 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X26Y50"
    )
    port map (
      ADR0 => UUT_N41,
      ADR1 => UUT_N351_0,
      ADR2 => N22_0,
      ADR3 => UUT_ack_count(2),
      O => UUT_N27_pack_1
    );
  UUT_out_i2cclk_mux000097_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux000097_5578,
      O => UUT_out_i2cclk_mux000097_0
    );
  UUT_out_i2cclk_mux000097_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N41_pack_1,
      O => UUT_N41
    );
  UUT_Dir_mux000051 : X_LUT4
    generic map(
      INIT => X"FEFE",
      LOC => "SLICE_X28Y54"
    )
    port map (
      ADR0 => UUT_ack_count(9),
      ADR1 => UUT_ack_count(11),
      ADR2 => UUT_ack_count(10),
      ADR3 => VCC,
      O => UUT_N41_pack_1
    );
  N153_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y45",
      PATHPULSE => 798 ps
    )
    port map (
      I => N153,
      O => N153_0
    );
  N153_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y45",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0011_pack_1,
      O => UUT_nstate_cmp_eq0011
    );
  UUT_Dir_mux000062 : X_LUT4
    generic map(
      INIT => X"4040",
      LOC => "SLICE_X27Y45"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2450,
      ADR1 => UUT_nstate_FFd2_2446,
      ADR2 => UUT_nstate_FFd4_2454,
      ADR3 => VCC,
      O => UUT_nstate_cmp_eq0011_pack_1
    );
  N114_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y42",
      PATHPULSE => 798 ps
    )
    port map (
      I => N114,
      O => N114_0
    );
  N114_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y42",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N64_pack_1,
      O => UUT_N64
    );
  UUT_Mtridata_in_i2c_not00011311 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X25Y42"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_nstate_FFd3_2450,
      ADR2 => VCC,
      ADR3 => UUT_nstate_FFd4_2454,
      O => UUT_N64_pack_1
    );
  UUT_Dir_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000224,
      O => UUT_Dir_DXMUX_5657
    );
  UUT_Dir_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000194_SW1_O_pack_1,
      O => UUT_Dir_mux0000194_SW1_O
    );
  UUT_Dir_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux000061,
      O => UUT_Dir_SRINV_5642
    );
  UUT_Dir_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_Dir_CLKINV_5641
    );
  N35_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => N35,
      O => N35_0
    );
  N35_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N511_pack_1,
      O => UUT_N511
    );
  UUT_Dir_mux000081 : X_LUT4
    generic map(
      INIT => X"C000",
      LOC => "SLICE_X29Y49"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(3),
      ADR2 => UUT_ack_count(6),
      ADR3 => UUT_ack_count(4),
      O => UUT_N511_pack_1
    );
  N56_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => N56,
      O => N56_0
    );
  N56_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y43",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000_5_1175_pack_1,
      O => UUT_pstate_mux0000_5_1175_2496
    );
  UUT_pstate_mux0000_5_1175 : X_LUT4
    generic map(
      INIT => X"00D8",
      LOC => "SLICE_X25Y43"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2450,
      ADR1 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q,
      ADR2 => UUT_pstate_mux0000_5_1155_0,
      ADR3 => UUT_N32_0,
      O => UUT_pstate_mux0000_5_1175_pack_1
    );
  UUT_ack_count_mux0000_10_23_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000_10_23_5731,
      O => UUT_ack_count_mux0000_10_23_0
    );
  UUT_ack_count_mux0000_10_23_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_cmp_eq0003_pack_1,
      O => UUT_ack_count_cmp_eq0003
    );
  UUT_ack_count_mux0000_0_41 : X_LUT4
    generic map(
      INIT => X"0002",
      LOC => "SLICE_X30Y50"
    )
    port map (
      ADR0 => UUT_N67_0,
      ADR1 => UUT_ack_count(0),
      ADR2 => UUT_ack_count(3),
      ADR3 => UUT_ack_count(6),
      O => UUT_ack_count_cmp_eq0003_pack_1
    );
  N96_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => N96,
      O => N96_0
    );
  N96_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => N49_pack_1,
      O => N49
    );
  UUT_shiftReg_cmp_eq00032_SW0 : X_LUT4
    generic map(
      INIT => X"FFCC",
      LOC => "SLICE_X22Y29"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(10),
      ADR2 => VCC,
      ADR3 => UUT_delay_count(6),
      O => N49_pack_1
    );
  UUT_writeCount_8_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X35Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(8),
      O => UUT_writeCount_8_DXMUX_5784
    );
  UUT_writeCount_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X35Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N35_pack_1,
      O => UUT_N35
    );
  UUT_writeCount_8_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X35Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_8_CLKINV_5768
    );
  UUT_writeCount_mux0000_10_21 : X_LUT4
    generic map(
      INIT => X"A000",
      LOC => "SLICE_X35Y4"
    )
    port map (
      ADR0 => UUT_Mtridata_in_i2c_mux0000119_0,
      ADR1 => VCC,
      ADR2 => UUT_ClkFallingEdge_2566,
      ADR3 => UUT_N13_0,
      O => UUT_N35_pack_1
    );
  UUT_writeCount_9_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(9),
      O => UUT_writeCount_9_DXMUX_5814
    );
  UUT_writeCount_9_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N11_pack_1,
      O => UUT_N11
    );
  UUT_writeCount_9_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X34Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_9_CLKINV_5799
    );
  UUT_writeCount_mux0000_10_11 : X_LUT4
    generic map(
      INIT => X"F2F0",
      LOC => "SLICE_X34Y4"
    )
    port map (
      ADR0 => UUT_N13_0,
      ADR1 => UUT_ClkFallingEdge_2566,
      ADR2 => UUT_delay_count_or0000,
      ADR3 => UUT_Mtridata_in_i2c_mux0000119_0,
      O => UUT_N11_pack_1
    );
  UUT_Mtrien_in_i2c_mux000061_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtrien_in_i2c_mux000061_5839,
      O => UUT_Mtrien_in_i2c_mux000061_0
    );
  UUT_Mtrien_in_i2c_mux000061_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtrien_in_i2c_mux000061_SW0_O_pack_1,
      O => UUT_Mtrien_in_i2c_mux000061_SW0_O
    );
  UUT_Mtrien_in_i2c_mux000061_SW0 : X_LUT4
    generic map(
      INIT => X"CFCF",
      LOC => "SLICE_X26Y44"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(1),
      ADR2 => UUT_N50_0,
      ADR3 => VCC,
      O => UUT_Mtrien_in_i2c_mux000061_SW0_O_pack_1
    );
  UUT_Mtrien_in_i2c_mux000055_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtrien_in_i2c_mux000055_5863,
      O => UUT_Mtrien_in_i2c_mux000055_0
    );
  UUT_Mtrien_in_i2c_mux000055_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0008_pack_1,
      O => UUT_nstate_cmp_eq0008
    );
  UUT_nstate_Out31 : X_LUT4
    generic map(
      INIT => X"0808",
      LOC => "SLICE_X27Y44"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2450,
      ADR1 => UUT_nstate_FFd2_2446,
      ADR2 => UUT_nstate_FFd4_2454,
      ADR3 => VCC,
      O => UUT_nstate_cmp_eq0008_pack_1
    );
  UUT_ack_count_0_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X29Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000_0_60,
      O => UUT_ack_count_0_DXMUX_5894
    );
  UUT_ack_count_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000_0_43_O_pack_1,
      O => UUT_ack_count_mux0000_0_43_O
    );
  UUT_ack_count_0_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X29Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000_0_28_5410,
      O => UUT_ack_count_0_SRINV_5879
    );
  UUT_ack_count_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X29Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_0_CLKINV_5878
    );
  UUT_shiftReg_cmp_eq0002_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0002,
      O => UUT_shiftReg_cmp_eq0002_0
    );
  UUT_shiftReg_cmp_eq0002_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux00012_SW0_O_pack_1,
      O => UUT_Dir_mux00012_SW0_O
    );
  UUT_Dir_mux00012_SW0 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X23Y34"
    )
    port map (
      ADR0 => UUT_delay_count(9),
      ADR1 => UUT_delay_count(0),
      ADR2 => UUT_delay_count(1),
      ADR3 => UUT_delay_count(10),
      O => UUT_Dir_mux00012_SW0_O_pack_1
    );
  UUT_shiftReg_2_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X26Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_2_11,
      O => UUT_shiftReg_2_DYMUX_7030
    );
  UUT_shiftReg_2_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_2_3_8194,
      O => UUT_shiftReg_2_SRINV_7022
    );
  UUT_shiftReg_2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_2_CLKINV_7021
    );
  UUT_shiftReg_3_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X26Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_3_23,
      O => UUT_shiftReg_3_DYMUX_7059
    );
  UUT_shiftReg_3_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_3_8_6499,
      O => UUT_shiftReg_3_SRINV_7051
    );
  UUT_shiftReg_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_3_CLKINV_7050
    );
  UUT_shiftReg_4_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_4_11,
      O => UUT_shiftReg_4_DYMUX_7080
    );
  UUT_shiftReg_4_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_4_3_7040,
      O => UUT_shiftReg_4_SRINV_7072
    );
  UUT_shiftReg_4_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_4_CLKINV_7071
    );
  UUT_writeCount_30_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(30),
      O => UUT_writeCount_30_DXMUX_7115
    );
  UUT_writeCount_30_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(1),
      O => UUT_writeCount_30_DYMUX_7104
    );
  UUT_writeCount_30_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X34Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_30_CLKINV_7096
    );
  UUT_writeCount_mux0000_1_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X34Y8"
    )
    port map (
      ADR0 => UUT_N11,
      ADR1 => UUT_writeCount_share0000(1),
      ADR2 => UUT_N35,
      ADR3 => UUT_writeCount(1),
      O => UUT_writeCount_mux0000(1)
    );
  UUT_writeCount_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(3),
      O => UUT_writeCount_3_DXMUX_7149
    );
  UUT_writeCount_3_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(2),
      O => UUT_writeCount_3_DYMUX_7138
    );
  UUT_writeCount_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_3_CLKINV_7130
    );
  UUT_writeCount_mux0000_2_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X36Y1"
    )
    port map (
      ADR0 => UUT_writeCount(2),
      ADR1 => UUT_N11,
      ADR2 => UUT_N35,
      ADR3 => UUT_writeCount_share0000(2),
      O => UUT_writeCount_mux0000(2)
    );
  UUT_writeCount_5_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(5),
      O => UUT_writeCount_5_DXMUX_7183
    );
  UUT_writeCount_5_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(4),
      O => UUT_writeCount_5_DYMUX_7172
    );
  UUT_writeCount_5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_5_CLKINV_7164
    );
  UUT_writeCount_mux0000_4_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X36Y3"
    )
    port map (
      ADR0 => UUT_N35,
      ADR1 => UUT_N11,
      ADR2 => UUT_writeCount_share0000(4),
      ADR3 => UUT_writeCount(4),
      O => UUT_writeCount_mux0000(4)
    );
  UUT_writeCount_7_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(7),
      O => UUT_writeCount_7_DXMUX_7217
    );
  UUT_writeCount_7_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(6),
      O => UUT_writeCount_7_DYMUX_7206
    );
  UUT_writeCount_7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_7_CLKINV_7198
    );
  UUT_writeCount_mux0000_6_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X36Y2"
    )
    port map (
      ADR0 => UUT_writeCount(6),
      ADR1 => UUT_N11,
      ADR2 => UUT_N35,
      ADR3 => UUT_writeCount_share0000(6),
      O => UUT_writeCount_mux0000(6)
    );
  UUT_prevClk_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_prevClk_mux0000,
      O => UUT_prevClk_DYMUX_7239
    );
  UUT_prevClk_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_prevClk_CLKINV_7230
    );
  UUT_prevClk_mux00001 : X_LUT4
    generic map(
      INIT => X"E8E8",
      LOC => "SLICE_X27Y30"
    )
    port map (
      ADR0 => UUT_prevClk_2675,
      ADR1 => UUT_ClkEdge(1),
      ADR2 => UUT_ClkEdge(0),
      ADR3 => VCC,
      O => UUT_prevClk_mux0000
    );
  UUT_ClkRisingEdge_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X26Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ClkRisingEdge_and00001,
      O => UUT_ClkRisingEdge_DYMUX_7267
    );
  UUT_ClkRisingEdge_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_prevClk_2675,
      O => UUT_ClkRisingEdge_SRINV_7257
    );
  UUT_ClkRisingEdge_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ClkRisingEdge_CLKINV_7256
    );
  UUT_pstate_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y42",
      PATHPULSE => 798 ps
    )
    port map (
      I => N13,
      O => N13_0
    );
  UUT_pstate_2_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X26Y42",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000(6),
      O => UUT_pstate_2_DYMUX_7291
    );
  UUT_pstate_2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y42",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_pstate_2_CLKINV_7283
    );
  UUT_pstate_mux0000_6_Q : X_LUT4
    generic map(
      INIT => X"FC55",
      LOC => "SLICE_X26Y42"
    )
    port map (
      ADR0 => N39_0,
      ADR1 => UUT_pstate_mux0000_5_115_0,
      ADR2 => N98_0,
      ADR3 => UUT_pstate(2),
      O => UUT_pstate_mux0000(6)
    );
  UUT_delay_count_0_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000_0_25,
      O => UUT_delay_count_0_DYMUX_7318
    );
  UUT_delay_count_0_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000_0_18_6824,
      O => UUT_delay_count_0_SRINV_7308
    );
  UUT_delay_count_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_0_CLKINV_7307
    );
  UUT_delay_count_1_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_or000032_7350,
      O => UUT_shiftReg_or000032_0
    );
  UUT_delay_count_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X19Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(1),
      O => UUT_delay_count_1_DYMUX_7341
    );
  UUT_delay_count_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X19Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_1_CLKINV_7333
    );
  UUT_delay_count_mux0000_1_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X19Y24"
    )
    port map (
      ADR0 => UUT_N4_0,
      ADR1 => UUT_delay_count_share0000(1),
      ADR2 => UUT_delay_count(1),
      ADR3 => UUT_N15_0,
      O => UUT_delay_count_mux0000(1)
    );
  UUT_delay_count_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(3),
      O => UUT_delay_count_3_DXMUX_7383
    );
  UUT_delay_count_3_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(2),
      O => UUT_delay_count_3_DYMUX_7372
    );
  UUT_delay_count_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_3_CLKINV_7364
    );
  UUT_delay_count_mux0000_2_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X20Y21"
    )
    port map (
      ADR0 => UUT_delay_count(2),
      ADR1 => UUT_N4_0,
      ADR2 => UUT_delay_count_or0000,
      ADR3 => UUT_delay_count_share0000(2),
      O => UUT_delay_count_mux0000(2)
    );
  UUT_delay_count_5_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(5),
      O => UUT_delay_count_5_DXMUX_7417
    );
  UUT_delay_count_5_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(4),
      O => UUT_delay_count_5_DYMUX_7406
    );
  UUT_delay_count_5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_5_CLKINV_7398
    );
  UUT_delay_count_mux0000_4_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X20Y22"
    )
    port map (
      ADR0 => UUT_delay_count(4),
      ADR1 => UUT_delay_count_or0000,
      ADR2 => UUT_delay_count_share0000(4),
      ADR3 => UUT_N4_0,
      O => UUT_delay_count_mux0000(4)
    );
  UUT_delay_count_7_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X22Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(7),
      O => UUT_delay_count_7_DXMUX_7451
    );
  UUT_delay_count_7_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X22Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(6),
      O => UUT_delay_count_7_DYMUX_7440
    );
  UUT_delay_count_7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_7_CLKINV_7432
    );
  UUT_delay_count_mux0000_6_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X22Y23"
    )
    port map (
      ADR0 => UUT_delay_count_or0000,
      ADR1 => UUT_delay_count_share0000(6),
      ADR2 => UUT_delay_count(6),
      ADR3 => UUT_N4_0,
      O => UUT_delay_count_mux0000(6)
    );
  UUT_delay_count_9_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(9),
      O => UUT_delay_count_9_DXMUX_7485
    );
  UUT_delay_count_9_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(8),
      O => UUT_delay_count_9_DYMUX_7474
    );
  UUT_delay_count_9_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_9_CLKINV_7466
    );
  UUT_delay_count_mux0000_8_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X20Y25"
    )
    port map (
      ADR0 => UUT_N15_0,
      ADR1 => UUT_N4_0,
      ADR2 => UUT_delay_count_share0000(8),
      ADR3 => UUT_delay_count(8),
      O => UUT_delay_count_mux0000(8)
    );
  UUT_ack_count_11_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y64",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(11),
      O => UUT_ack_count_11_DXMUX_7519
    );
  UUT_ack_count_11_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y64",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(10),
      O => UUT_ack_count_11_DYMUX_7508
    );
  UUT_ack_count_11_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y64",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_11_CLKINV_7500
    );
  UUT_ack_count_mux0000_10_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X36Y64"
    )
    port map (
      ADR0 => UUT_N3_0,
      ADR1 => UUT_ack_count(10),
      ADR2 => UUT_ack_count_share0000(10),
      ADR3 => UUT_N14_0,
      O => UUT_ack_count_mux0000(10)
    );
  UUT_shiftReg_mux0000_0_5 : X_LUT4
    generic map(
      INIT => X"FF80",
      LOC => "SLICE_X22Y32"
    )
    port map (
      ADR0 => UUT_out_i2c,
      ADR1 => UUT_nstate_cmp_eq0010,
      ADR2 => UUT_ClkRisingEdge_2465,
      ADR3 => UUT_nstate_cmp_eq0005_0,
      O => UUT_shiftReg_mux0000_0_5_O_pack_1
    );
  UUT_shiftReg_mux0000_3_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_3_5_O_pack_1,
      O => UUT_shiftReg_mux0000_3_5_O
    );
  UUT_shiftReg_mux0000_3_5 : X_LUT4
    generic map(
      INIT => X"EAAA",
      LOC => "SLICE_X23Y32"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0005_0,
      ADR1 => UUT_ClkRisingEdge_2465,
      ADR2 => UUT_nstate_cmp_eq0010,
      ADR3 => UUT_shiftReg(2),
      O => UUT_shiftReg_mux0000_3_5_O_pack_1
    );
  UUT_shiftReg_5_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_5_1_6527,
      O => UUT_shiftReg_5_DXMUX_6530
    );
  UUT_shiftReg_5_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_5_SW0_O_pack_1,
      O => UUT_shiftReg_mux0000_5_SW0_O
    );
  UUT_shiftReg_5_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0005_0,
      O => UUT_shiftReg_5_SRINV_6514
    );
  UUT_shiftReg_5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_5_CLKINV_6513
    );
  UUT_shiftReg_mux0000_6_5_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_6_3_O_pack_1,
      O => UUT_shiftReg_mux0000_6_3_O
    );
  UUT_shiftReg_mux0000_6_3 : X_LUT4
    generic map(
      INIT => X"C000",
      LOC => "SLICE_X22Y33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_nstate_cmp_eq0010,
      ADR2 => UUT_ClkRisingEdge_2465,
      ADR3 => UUT_shiftReg(5),
      O => UUT_shiftReg_mux0000_6_3_O_pack_1
    );
  UUT_shiftReg_7_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_7_1_6584,
      O => UUT_shiftReg_7_DXMUX_6587
    );
  UUT_shiftReg_7_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_119_O_pack_1,
      O => UUT_shiftReg_mux0000_0_119_O
    );
  UUT_shiftReg_7_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0005_0,
      O => UUT_shiftReg_7_SRINV_6572
    );
  UUT_shiftReg_7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_7_CLKINV_6571
    );
  UUT_N38_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N38,
      O => UUT_N38_0
    );
  UUT_N38_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => N53_pack_1,
      O => N53
    );
  UUT_shiftReg_cmp_eq00031_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X21Y29"
    )
    port map (
      ADR0 => UUT_delay_count(11),
      ADR1 => UUT_delay_count(13),
      ADR2 => UUT_delay_count(14),
      ADR3 => UUT_delay_count(12),
      O => N53_pack_1
    );
  UUT_N112_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N112,
      O => UUT_N112_0
    );
  UUT_N112_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_mux0000_4_1_SW0_O_pack_1,
      O => UUT_counter_mux0000_4_1_SW0_O
    );
  UUT_counter_mux0000_4_1_SW0 : X_LUT4
    generic map(
      INIT => X"5500",
      LOC => "SLICE_X24Y36"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2465,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_nstate_FFd2_2446,
      O => UUT_counter_mux0000_4_1_SW0_O_pack_1
    );
  N128_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => N128,
      O => N128_0
    );
  N128_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_mux000027_SW0_SW0_O_pack_1,
      O => UUT_Mtridata_in_i2c_mux000027_SW0_SW0_O
    );
  UUT_Mtridata_in_i2c_mux000027_SW0_SW0 : X_LUT4
    generic map(
      INIT => X"FF77",
      LOC => "SLICE_X26Y40"
    )
    port map (
      ADR0 => UUT_ack_count(6),
      ADR1 => UUT_nstate_FFd1_2447,
      ADR2 => VCC,
      ADR3 => UUT_ack_count(1),
      O => UUT_Mtridata_in_i2c_mux000027_SW0_SW0_O_pack_1
    );
  N86_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => N86,
      O => N86_0
    );
  N86_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_111_SW1_O_pack_1,
      O => UUT_shiftReg_mux0000_0_111_SW1_O
    );
  UUT_shiftReg_mux0000_0_111_SW1 : X_LUT4
    generic map(
      INIT => X"BFBB",
      LOC => "SLICE_X23Y28"
    )
    port map (
      ADR0 => UUT_ClkFallingEdge_2566,
      ADR1 => UUT_shiftReg_mux0000_0_114_0,
      ADR2 => N71_0,
      ADR3 => UUT_shiftReg_cmp_eq0001,
      O => UUT_shiftReg_mux0000_0_111_SW1_O_pack_1
    );
  UUT_N15_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N15,
      O => UUT_N15_0
    );
  UUT_N15_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000_11_1_SW1_O_pack_1,
      O => UUT_delay_count_mux0000_11_1_SW1_O
    );
  UUT_delay_count_mux0000_11_1_SW1 : X_LUT4
    generic map(
      INIT => X"0008",
      LOC => "SLICE_X22Y27"
    )
    port map (
      ADR0 => UUT_N32_0,
      ADR1 => UUT_delay_count_and0000_0,
      ADR2 => UUT_delay_count(2),
      ADR3 => UUT_ClkFallingEdge_2566,
      O => UUT_delay_count_mux0000_11_1_SW1_O_pack_1
    );
  UUT_out_i2cclk_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X28Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000263,
      O => UUT_out_i2cclk_DXMUX_6740
    );
  UUT_out_i2cclk_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000204_O_pack_1,
      O => UUT_out_i2cclk_mux0000204_O
    );
  UUT_out_i2cclk_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X28Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000104_6241,
      O => UUT_out_i2cclk_SRINV_6725
    );
  UUT_out_i2cclk_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X28Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_out_i2cclk_CLKINV_6724
    );
  UUT_delay_count_and0000_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_and0000,
      O => UUT_delay_count_and0000_0
    );
  UUT_delay_count_and0000_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq00031_SW2_O_pack_1,
      O => UUT_shiftReg_cmp_eq00031_SW2_O
    );
  UUT_shiftReg_cmp_eq00031_SW2 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X20Y26"
    )
    port map (
      ADR0 => UUT_delay_count(15),
      ADR1 => UUT_delay_count(5),
      ADR2 => UUT_delay_count(3),
      ADR3 => UUT_delay_count(1),
      O => UUT_shiftReg_cmp_eq00031_SW2_O_pack_1
    );
  UUT_nstate_FFd4_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_FXMUX_6797,
      O => UUT_nstate_FFd4_DXMUX_6798
    );
  UUT_nstate_FFd4_FXMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_In79,
      O => UUT_nstate_FFd4_FXMUX_6797
    );
  UUT_nstate_FFd4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_In77_O_pack_1,
      O => UUT_nstate_FFd4_In77_O
    );
  UUT_nstate_FFd4_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_In0_0,
      O => UUT_nstate_FFd4_SRINV_6781
    );
  UUT_nstate_FFd4_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_nstate_FFd4_CLKINV_6780
    );
  UUT_delay_count_mux0000_0_18_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000_0_18_SW0_O_pack_1,
      O => UUT_delay_count_mux0000_0_18_SW0_O
    );
  UUT_delay_count_mux0000_0_18_SW0 : X_LUT4
    generic map(
      INIT => X"0800",
      LOC => "SLICE_X22Y26"
    )
    port map (
      ADR0 => UUT_N32_0,
      ADR1 => UUT_ClkFallingEdge_2566,
      ADR2 => UUT_delay_count(2),
      ADR3 => UUT_nstate_FFd3_2450,
      O => UUT_delay_count_mux0000_0_18_SW0_O_pack_1
    );
  UUT_delay_count_mux0000_0_117_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000_0_117_6848,
      O => UUT_delay_count_mux0000_0_117_0
    );
  UUT_delay_count_mux0000_0_117_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000_0_181_O_pack_1,
      O => UUT_delay_count_mux0000_0_181_O
    );
  UUT_delay_count_mux0000_0_181 : X_LUT4
    generic map(
      INIT => X"5F5F",
      LOC => "SLICE_X18Y28"
    )
    port map (
      ADR0 => UUT_delay_count(9),
      ADR1 => VCC,
      ADR2 => UUT_delay_count(6),
      ADR3 => VCC,
      O => UUT_delay_count_mux0000_0_181_O_pack_1
    );
  UUT_N4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N4,
      O => UUT_N4_0
    );
  UUT_N4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000_0_146_O_pack_1,
      O => UUT_delay_count_mux0000_0_146_O
    );
  UUT_delay_count_mux0000_0_146 : X_LUT4
    generic map(
      INIT => X"FFEF",
      LOC => "SLICE_X23Y29"
    )
    port map (
      ADR0 => UUT_delay_count_mux0000_0_122_0,
      ADR1 => UUT_N331_0,
      ADR2 => UUT_delay_count_and0000_0,
      ADR3 => UUT_delay_count_mux0000_0_117_0,
      O => UUT_delay_count_mux0000_0_146_O_pack_1
    );
  UUT_delay_count_11_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(11),
      O => UUT_delay_count_11_DXMUX_6905
    );
  UUT_delay_count_11_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(10),
      O => UUT_delay_count_11_DYMUX_6894
    );
  UUT_delay_count_11_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_11_CLKINV_6886
    );
  UUT_delay_count_mux0000_10_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X20Y24"
    )
    port map (
      ADR0 => UUT_delay_count_share0000(10),
      ADR1 => UUT_delay_count(10),
      ADR2 => UUT_delay_count_or0000,
      ADR3 => UUT_N4_0,
      O => UUT_delay_count_mux0000(10)
    );
  UUT_delay_count_13_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X18Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(13),
      O => UUT_delay_count_13_DXMUX_6939
    );
  UUT_delay_count_13_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X18Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(12),
      O => UUT_delay_count_13_DYMUX_6928
    );
  UUT_delay_count_13_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X18Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_13_CLKINV_6920
    );
  UUT_delay_count_mux0000_12_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X18Y26"
    )
    port map (
      ADR0 => UUT_delay_count_share0000(12),
      ADR1 => UUT_N4_0,
      ADR2 => UUT_delay_count(12),
      ADR3 => UUT_N15_0,
      O => UUT_delay_count_mux0000(12)
    );
  UUT_delay_count_15_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(15),
      O => UUT_delay_count_15_DXMUX_6973
    );
  UUT_delay_count_15_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(14),
      O => UUT_delay_count_15_DYMUX_6962
    );
  UUT_delay_count_15_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_15_CLKINV_6954
    );
  UUT_delay_count_mux0000_14_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X20Y27"
    )
    port map (
      ADR0 => UUT_delay_count(14),
      ADR1 => UUT_N15_0,
      ADR2 => UUT_N4_0,
      ADR3 => UUT_delay_count_share0000(14),
      O => UUT_delay_count_mux0000(14)
    );
  UUT_shiftReg_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_mux000054_7007,
      O => UUT_Mtridata_in_i2c_mux000054_0
    );
  UUT_shiftReg_0_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X22Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_231,
      O => UUT_shiftReg_0_DYMUX_6997
    );
  UUT_shiftReg_0_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_8_6475,
      O => UUT_shiftReg_0_SRINV_6989
    );
  UUT_shiftReg_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_0_CLKINV_6988
    );
  UUT_ack_count_1_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtrien_in_i2c_mux000041_7550,
      O => UUT_Mtrien_in_i2c_mux000041_0
    );
  UUT_ack_count_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X30Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(1),
      O => UUT_ack_count_1_DYMUX_7540
    );
  UUT_ack_count_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X30Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_1_CLKINV_7532
    );
  UUT_ack_count_mux0000_1_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X30Y53"
    )
    port map (
      ADR0 => UUT_ack_count_share0000(1),
      ADR1 => UUT_N3_0,
      ADR2 => UUT_N14_0,
      ADR3 => UUT_ack_count(1),
      O => UUT_ack_count_mux0000(1)
    );
  UUT_ack_count_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(3),
      O => UUT_ack_count_3_DXMUX_7583
    );
  UUT_ack_count_3_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(2),
      O => UUT_ack_count_3_DYMUX_7572
    );
  UUT_ack_count_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_3_CLKINV_7564
    );
  UUT_ack_count_mux0000_2_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X36Y60"
    )
    port map (
      ADR0 => UUT_ack_count(2),
      ADR1 => UUT_N3_0,
      ADR2 => UUT_ack_count_share0000(2),
      ADR3 => UUT_N14_0,
      O => UUT_ack_count_mux0000(2)
    );
  UUT_ack_count_5_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(5),
      O => UUT_ack_count_5_DXMUX_7617
    );
  UUT_ack_count_5_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(4),
      O => UUT_ack_count_5_DYMUX_7606
    );
  UUT_ack_count_5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_5_CLKINV_7598
    );
  UUT_ack_count_mux0000_4_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X36Y61"
    )
    port map (
      ADR0 => UUT_ack_count(4),
      ADR1 => UUT_N3_0,
      ADR2 => UUT_N211_0,
      ADR3 => UUT_ack_count_share0000(4),
      O => UUT_ack_count_mux0000(4)
    );
  UUT_ack_count_7_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y62",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(7),
      O => UUT_ack_count_7_DXMUX_7651
    );
  UUT_ack_count_7_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y62",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(6),
      O => UUT_ack_count_7_DYMUX_7640
    );
  UUT_ack_count_7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y62",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_7_CLKINV_7632
    );
  UUT_ack_count_mux0000_6_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X36Y62"
    )
    port map (
      ADR0 => UUT_N211_0,
      ADR1 => UUT_ack_count(6),
      ADR2 => UUT_ack_count_share0000(6),
      ADR3 => UUT_N3_0,
      O => UUT_ack_count_mux0000(6)
    );
  UUT_ack_count_9_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y63",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(9),
      O => UUT_ack_count_9_DXMUX_7685
    );
  UUT_ack_count_9_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y63",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(8),
      O => UUT_ack_count_9_DYMUX_7674
    );
  UUT_ack_count_9_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y63",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_9_CLKINV_7666
    );
  UUT_ack_count_mux0000_8_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X36Y63"
    )
    port map (
      ADR0 => UUT_ack_count(8),
      ADR1 => UUT_N14_0,
      ADR2 => UUT_N3_0,
      ADR3 => UUT_ack_count_share0000(8),
      O => UUT_ack_count_mux0000(8)
    );
  UUT_writeCount_11_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(11),
      O => UUT_writeCount_11_DXMUX_7719
    );
  UUT_writeCount_11_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(10),
      O => UUT_writeCount_11_DYMUX_7708
    );
  UUT_writeCount_11_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_11_CLKINV_7700
    );
  UUT_writeCount_mux0000_10_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X36Y4"
    )
    port map (
      ADR0 => UUT_writeCount(10),
      ADR1 => UUT_N11,
      ADR2 => UUT_N35,
      ADR3 => UUT_writeCount_share0000(10),
      O => UUT_writeCount_mux0000(10)
    );
  UUT_writeCount_13_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(13),
      O => UUT_writeCount_13_DXMUX_7753
    );
  UUT_writeCount_13_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(12),
      O => UUT_writeCount_13_DYMUX_7742
    );
  UUT_writeCount_13_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X34Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_13_CLKINV_7734
    );
  UUT_writeCount_mux0000_12_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X34Y7"
    )
    port map (
      ADR0 => UUT_N11,
      ADR1 => UUT_writeCount(12),
      ADR2 => UUT_N35,
      ADR3 => UUT_writeCount_share0000(12),
      O => UUT_writeCount_mux0000(12)
    );
  UUT_writeCount_21_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(21),
      O => UUT_writeCount_21_DXMUX_7787
    );
  UUT_writeCount_21_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(20),
      O => UUT_writeCount_21_DYMUX_7776
    );
  UUT_writeCount_21_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_21_CLKINV_7768
    );
  UUT_writeCount_mux0000_20_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X36Y9"
    )
    port map (
      ADR0 => UUT_writeCount(20),
      ADR1 => UUT_N35,
      ADR2 => UUT_N11,
      ADR3 => UUT_writeCount_share0000(20),
      O => UUT_writeCount_mux0000(20)
    );
  UUT_writeCount_15_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(15),
      O => UUT_writeCount_15_DXMUX_7821
    );
  UUT_writeCount_15_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(14),
      O => UUT_writeCount_15_DYMUX_7810
    );
  UUT_writeCount_15_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_15_CLKINV_7802
    );
  UUT_writeCount_mux0000_14_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X36Y6"
    )
    port map (
      ADR0 => UUT_N35,
      ADR1 => UUT_N11,
      ADR2 => UUT_writeCount(14),
      ADR3 => UUT_writeCount_share0000(14),
      O => UUT_writeCount_mux0000(14)
    );
  UUT_writeCount_23_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(23),
      O => UUT_writeCount_23_DXMUX_7855
    );
  UUT_writeCount_23_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(22),
      O => UUT_writeCount_23_DYMUX_7844
    );
  UUT_writeCount_23_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_23_CLKINV_7836
    );
  UUT_writeCount_mux0000_22_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X36Y11"
    )
    port map (
      ADR0 => UUT_N11,
      ADR1 => UUT_writeCount(22),
      ADR2 => UUT_N35,
      ADR3 => UUT_writeCount_share0000(22),
      O => UUT_writeCount_mux0000(22)
    );
  UUT_writeCount_17_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(17),
      O => UUT_writeCount_17_DXMUX_7889
    );
  UUT_writeCount_17_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(16),
      O => UUT_writeCount_17_DYMUX_7878
    );
  UUT_writeCount_17_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_17_CLKINV_7870
    );
  UUT_writeCount_mux0000_16_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X36Y8"
    )
    port map (
      ADR0 => UUT_N35,
      ADR1 => UUT_writeCount_share0000(16),
      ADR2 => UUT_N11,
      ADR3 => UUT_writeCount(16),
      O => UUT_writeCount_mux0000(16)
    );
  UUT_writeCount_25_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(25),
      O => UUT_writeCount_25_DXMUX_7923
    );
  UUT_writeCount_25_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(24),
      O => UUT_writeCount_25_DYMUX_7912
    );
  UUT_writeCount_25_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_25_CLKINV_7904
    );
  UUT_writeCount_mux0000_24_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X36Y13"
    )
    port map (
      ADR0 => UUT_N35,
      ADR1 => UUT_writeCount_share0000(24),
      ADR2 => UUT_N11,
      ADR3 => UUT_writeCount(24),
      O => UUT_writeCount_mux0000(24)
    );
  UUT_writeCount_19_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(19),
      O => UUT_writeCount_19_DXMUX_7957
    );
  UUT_writeCount_19_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(18),
      O => UUT_writeCount_19_DYMUX_7946
    );
  UUT_writeCount_19_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_19_CLKINV_7938
    );
  UUT_writeCount_mux0000_18_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X36Y7"
    )
    port map (
      ADR0 => UUT_N11,
      ADR1 => UUT_writeCount(18),
      ADR2 => UUT_N35,
      ADR3 => UUT_writeCount_share0000(18),
      O => UUT_writeCount_mux0000(18)
    );
  UUT_writeCount_27_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(27),
      O => UUT_writeCount_27_DXMUX_7991
    );
  UUT_writeCount_27_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(26),
      O => UUT_writeCount_27_DYMUX_7980
    );
  UUT_writeCount_27_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_27_CLKINV_7972
    );
  UUT_writeCount_mux0000_26_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X36Y12"
    )
    port map (
      ADR0 => UUT_N35,
      ADR1 => UUT_writeCount(26),
      ADR2 => UUT_N11,
      ADR3 => UUT_writeCount_share0000(26),
      O => UUT_writeCount_mux0000(26)
    );
  UUT_writeCount_29_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(29),
      O => UUT_writeCount_29_DXMUX_8025
    );
  UUT_writeCount_29_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X36Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(28),
      O => UUT_writeCount_29_DYMUX_8014
    );
  UUT_writeCount_29_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X36Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_29_CLKINV_8006
    );
  UUT_writeCount_mux0000_28_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X36Y14"
    )
    port map (
      ADR0 => UUT_N35,
      ADR1 => UUT_writeCount_share0000(28),
      ADR2 => UUT_N11,
      ADR3 => UUT_writeCount(28),
      O => UUT_writeCount_mux0000(28)
    );
  UUT_Mtridata_in_i2c_mux0000119_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_mux0000119_8050,
      O => UUT_Mtridata_in_i2c_mux0000119_0
    );
  UUT_Mtridata_in_i2c_mux0000119_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N32,
      O => UUT_N32_0
    );
  UUT_Dir_mux000031 : X_LUT4
    generic map(
      INIT => X"FAFA",
      LOC => "SLICE_X26Y29"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => VCC,
      ADR2 => UUT_nstate_FFd4_2454,
      ADR3 => VCC,
      O => UUT_N32
    );
  UUT_shiftReg_mux0000_0_25_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_25_8074,
      O => UUT_shiftReg_mux0000_0_25_0
    );
  UUT_shiftReg_mux0000_0_25_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_mux000065_8066,
      O => UUT_Mtridata_in_i2c_mux000065_0
    );
  UUT_Mtridata_in_i2c_mux000065 : X_LUT4
    generic map(
      INIT => X"EACC",
      LOC => "SLICE_X22Y34"
    )
    port map (
      ADR0 => UUT_shiftReg_cmp_eq0002_0,
      ADR1 => UUT_Mtridata_in_i2c_mux000054_0,
      ADR2 => UUT_shiftReg_or0000,
      ADR3 => UUT_shiftReg_and0000_0,
      O => UUT_Mtridata_in_i2c_mux000065_8066
    );
  UUT_out_i2cclk_mux0000131_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y47",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000131_8098,
      O => UUT_out_i2cclk_mux0000131_0
    );
  UUT_out_i2cclk_mux0000131_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y47",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N65,
      O => UUT_N65_0
    );
  UUT_pstate_mux0000_5_112 : X_LUT4
    generic map(
      INIT => X"70F0",
      LOC => "SLICE_X27Y47"
    )
    port map (
      ADR0 => UUT_ack_count(0),
      ADR1 => UUT_ack_count(5),
      ADR2 => UUT_nstate_FFd1_2447,
      ADR3 => N35_0,
      O => UUT_N65
    );
  UUT_in_i2c_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_mux000078_8113,
      O => UUT_Mtridata_in_i2c_mux000078_0
    );
  UUT_Mtridata_in_i2c_mux000078 : X_LUT4
    generic map(
      INIT => X"0404",
      LOC => "SLICE_X23Y38"
    )
    port map (
      ADR0 => UUT_shiftReg_cmp_eq0001,
      ADR1 => UUT_Mtridata_in_i2c_2515,
      ADR2 => UUT_ClkFallingEdge_2566,
      ADR3 => VCC,
      O => UUT_Mtridata_in_i2c_mux000078_8113
    );
  UUT_N327_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y46",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N327_8146,
      O => UUT_N327_0
    );
  UUT_N327_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y46",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux000058_8139,
      O => UUT_Dir_mux000058_0
    );
  UUT_Dir_mux000058 : X_LUT4
    generic map(
      INIT => X"2000",
      LOC => "SLICE_X29Y46"
    )
    port map (
      ADR0 => UUT_ack_count(3),
      ADR1 => UUT_N41,
      ADR2 => UUT_ack_count(6),
      ADR3 => UUT_ack_count(4),
      O => UUT_Dir_mux000058_8139
    );
  UUT_Mtridata_in_i2c_not00012_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mtridata_in_i2c_not00012_8170,
      O => UUT_Mtridata_in_i2c_not00012_0
    );
  UUT_Mtridata_in_i2c_not00012_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux00002_8163,
      O => UUT_out_i2cclk_mux00002_0
    );
  UUT_out_i2cclk_mux00002 : X_LUT4
    generic map(
      INIT => X"FFFC",
      LOC => "SLICE_X26Y49"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_nstate_FFd1_2447,
      ADR2 => UUT_nstate_FFd2_2446,
      ADR3 => UUT_nstate_FFd3_2450,
      O => UUT_out_i2cclk_mux00002_8163
    );
  UUT_counter_mux0000_4_111 : X_LUT4
    generic map(
      INIT => X"E2C0",
      LOC => "SLICE_X24Y35"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0010,
      ADR1 => UUT_counter(0),
      ADR2 => UUT_N112_0,
      ADR3 => UUT_ClkRisingEdge_2465,
      O => UUT_counter_mux0000_4_11
    );
  N116_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => N116,
      O => N116_0
    );
  N116_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N351,
      O => UUT_N351_0
    );
  UUT_ack_count_or000421 : X_LUT4
    generic map(
      INIT => X"FFFC",
      LOC => "SLICE_X26Y48"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(4),
      ADR2 => UUT_ack_count(3),
      ADR3 => UUT_ack_count(0),
      O => UUT_N351
    );
  CLK_sI2C_Clk_cmp_eq00007_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X32Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq00007_8230,
      O => CLK_sI2C_Clk_cmp_eq00007_0
    );
  CLK_sI2C_Clk_cmp_eq00007 : X_LUT4
    generic map(
      INIT => X"2000",
      LOC => "SLICE_X32Y34"
    )
    port map (
      ADR0 => CLK_clk_div(5),
      ADR1 => CLK_clk_div(7),
      ADR2 => CLK_clk_div(6),
      ADR3 => CLK_clk_div(4),
      O => CLK_sI2C_Clk_cmp_eq00007_8230
    );
  UUT_Dir_mux0000169_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000169_8254,
      O => UUT_Dir_mux0000169_0
    );
  UUT_Dir_mux0000169_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000143_pack_1,
      O => UUT_Dir_mux0000143_2682
    );
  UUT_Dir_mux0000143 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X23Y30"
    )
    port map (
      ADR0 => UUT_delay_count(9),
      ADR1 => UUT_delay_count(4),
      ADR2 => UUT_delay_count(6),
      ADR3 => UUT_delay_count(7),
      O => UUT_Dir_mux0000143_pack_1
    );
  N22_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => N22,
      O => N22_0
    );
  N22_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N53,
      O => UUT_N53_0
    );
  UUT_Dir_mux0000411 : X_LUT4
    generic map(
      INIT => X"0003",
      LOC => "SLICE_X27Y50"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(7),
      ADR2 => UUT_ack_count(2),
      ADR3 => UUT_ack_count(8),
      O => UUT_N53
    );
  N71_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => N71,
      O => N71_0
    );
  N71_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000148_8295,
      O => UUT_Dir_mux0000148_0
    );
  UUT_Dir_mux0000148 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X22Y31"
    )
    port map (
      ADR0 => UUT_delay_count(0),
      ADR1 => UUT_delay_count(10),
      ADR2 => UUT_delay_count(2),
      ADR3 => UUT_delay_count(1),
      O => UUT_Dir_mux0000148_8295
    );
  UUT_nstate_cmp_eq0005_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0005,
      O => UUT_nstate_cmp_eq0005_0
    );
  UUT_nstate_cmp_eq0005_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N69,
      O => UUT_N69_0
    );
  UUT_Dir_mux0000432 : X_LUT4
    generic map(
      INIT => X"5050",
      LOC => "SLICE_X25Y36"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2450,
      ADR1 => VCC,
      ADR2 => UUT_nstate_FFd4_2454,
      ADR3 => VCC,
      O => UUT_N69
    );
  UUT_counter_0_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X26Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_mux0000_4_24_8354,
      O => UUT_counter_0_DXMUX_8357
    );
  UUT_counter_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => N169_pack_1,
      O => N169
    );
  UUT_counter_0_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_mux0000_4_11,
      O => UUT_counter_0_SRINV_8342
    );
  UUT_counter_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_counter_0_CLKINV_8341
    );
  UUT_pstate_mux0000_5_1155_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y45",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000_5_1155_8371,
      O => UUT_pstate_mux0000_5_1155_0
    );
  UUT_pstate_mux0000_5_1155 : X_LUT4
    generic map(
      INIT => X"F0FF",
      LOC => "SLICE_X24Y45"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => CLK_sI2C_Clk_2469,
      ADR3 => SW_3_IBUF_2443,
      O => UUT_pstate_mux0000_5_1155_8371
    );
  UUT_delay_count_mux0000_0_122_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000_0_122_8395,
      O => UUT_delay_count_mux0000_0_122_0
    );
  UUT_delay_count_mux0000_0_122_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => N58,
      O => N58_0
    );
  UUT_shiftReg_and00001_SW0 : X_LUT4
    generic map(
      INIT => X"000F",
      LOC => "SLICE_X22Y30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(2),
      ADR3 => UUT_delay_count(5),
      O => N58
    );
  CLK_sI2C_Clk_DYMUX : X_INV
    generic map(
      LOC => "SLICE_X28Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_2469,
      O => CLK_sI2C_Clk_DYMUX_8405
    );
  CLK_sI2C_Clk_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X28Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => CLK_sI2C_Clk_CLKINV_8403
    );
  CLK_sI2C_Clk_CEINV : X_BUF
    generic map(
      LOC => "SLICE_X28Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq0000_0,
      O => CLK_sI2C_Clk_CEINV_8402
    );
  UUT_out_i2cclk_mux0000118_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000118_8431,
      O => UUT_out_i2cclk_mux0000118_0
    );
  UUT_out_i2cclk_mux0000118_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => N159,
      O => N159_0
    );
  UUT_out_i2cclk_mux000097_SW0 : X_LUT4
    generic map(
      INIT => X"F7FF",
      LOC => "SLICE_X28Y55"
    )
    port map (
      ADR0 => UUT_ack_count(5),
      ADR1 => UUT_nstate_FFd1_2447,
      ADR2 => UUT_ack_count(1),
      ADR3 => UUT_ack_count(4),
      O => N159
    );
  UUT_out_i2cclk_mux0000162_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000162_8455,
      O => UUT_out_i2cclk_mux0000162_0
    );
  UUT_out_i2cclk_mux0000162_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => N181,
      O => N181_0
    );
  UUT_out_i2cclk_mux000097_SW1 : X_LUT4
    generic map(
      INIT => X"FFF7",
      LOC => "SLICE_X29Y54"
    )
    port map (
      ADR0 => UUT_ack_count(6),
      ADR1 => UUT_ack_count(3),
      ADR2 => UUT_ack_count(7),
      ADR3 => UUT_ack_count(2),
      O => N181
    );
  CLK_sI2C_Clk_cmp_eq0000_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X32Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq0000,
      O => CLK_sI2C_Clk_cmp_eq0000_0
    );
  CLK_sI2C_Clk_cmp_eq0000_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X32Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq000016_pack_1,
      O => CLK_sI2C_Clk_cmp_eq000016_2684
    );
  CLK_sI2C_Clk_cmp_eq000016 : X_LUT4
    generic map(
      INIT => X"0200",
      LOC => "SLICE_X32Y33"
    )
    port map (
      ADR0 => CLK_clk_div(2),
      ADR1 => CLK_clk_div(1),
      ADR2 => CLK_clk_div(0),
      ADR3 => CLK_clk_div(3),
      O => CLK_sI2C_Clk_cmp_eq000016_pack_1
    );
  N146_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => N146,
      O => N146_0
    );
  UUT_shiftReg_mux0000_0_111_SW0_SW1_SW0 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X23Y26"
    )
    port map (
      ADR0 => UUT_delay_count(4),
      ADR1 => UUT_delay_count(2),
      ADR2 => UUT_delay_count(9),
      ADR3 => UUT_delay_count(7),
      O => N146
    );
  UUT_ClkEdge_1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ClkEdge(0),
      O => UUT_ClkEdge_1_DXMUX_8506
    );
  UUT_ClkEdge_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_2469,
      O => UUT_ClkEdge_1_DYMUX_8501
    );
  UUT_ClkEdge_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ClkEdge_1_CLKINV_8499
    );
  UUT_Dir_mux000082_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux000082_8531,
      O => UUT_Dir_mux000082_0
    );
  UUT_Dir_mux000082_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => N183_pack_1,
      O => N183
    );
  UUT_Dir_mux000082_SW1 : X_LUT4
    generic map(
      INIT => X"FFCD",
      LOC => "SLICE_X23Y35"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2454,
      ADR1 => UUT_delay_count(2),
      ADR2 => UUT_nstate_FFd2_2446,
      ADR3 => UUT_delay_count(5),
      O => N183_pack_1
    );
  UUT_nstate_cmp_eq0006_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y45",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0006,
      O => UUT_nstate_cmp_eq0006_0
    );
  UUT_nstate_cmp_eq0006_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y45",
      PATHPULSE => 798 ps
    )
    port map (
      I => N134,
      O => N134_0
    );
  UUT_Dir_mux0000194_SW0_SW0 : X_LUT4
    generic map(
      INIT => X"0020",
      LOC => "SLICE_X26Y45"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2454,
      ADR1 => UUT_ack_count(1),
      ADR2 => UUT_nstate_FFd2_2446,
      ADR3 => UUT_nstate_FFd3_2450,
      O => N134
    );
  UUT_nstate_FFd4_In0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_In0_8567,
      O => UUT_nstate_FFd4_In0_0
    );
  UUT_nstate_FFd4_In0 : X_LUT4
    generic map(
      INIT => X"C0C0",
      LOC => "SLICE_X26Y38"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_nstate_cmp_eq0010,
      ADR2 => UUT_nstate_cmp_eq0000_0,
      ADR3 => VCC,
      O => UUT_nstate_FFd4_In0_8567
    );
  N123_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => N123,
      O => N123_0
    );
  N123_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => N95,
      O => N95_0
    );
  UUT_shiftReg_mux0000_0_111_SW0_SW0 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X25Y28"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => UUT_nstate_FFd4_2454,
      ADR2 => UUT_nstate_FFd3_2450,
      ADR3 => UUT_ClkFallingEdge_2566,
      O => N95
    );
  UUT_nstate_cmp_eq0012_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0012,
      O => UUT_nstate_cmp_eq0012_0
    );
  UUT_nstate_cmp_eq0012_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N26,
      O => UUT_N26_0
    );
  UUT_shiftReg_mux0000_0_211 : X_LUT4
    generic map(
      INIT => X"6060",
      LOC => "SLICE_X25Y29"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => UUT_nstate_FFd4_2454,
      ADR2 => UUT_nstate_FFd3_2450,
      ADR3 => VCC,
      O => UUT_N26
    );
  N102_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => N102,
      O => N102_0
    );
  N102_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_240_pack_1,
      O => UUT_shiftReg_mux0000_0_240_2471
    );
  UUT_shiftReg_mux0000_0_240 : X_LUT4
    generic map(
      INIT => X"EA2A",
      LOC => "SLICE_X24Y29"
    )
    port map (
      ADR0 => N95_0,
      ADR1 => UUT_shiftReg_cmp_eq0001,
      ADR2 => UUT_delay_count_and0000_0,
      ADR3 => N96_0,
      O => UUT_shiftReg_mux0000_0_240_pack_1
    );
  UUT_shiftReg_mux0000_0_114_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_114,
      O => UUT_shiftReg_mux0000_0_114_0
    );
  UUT_shiftReg_mux0000_0_237 : X_LUT4
    generic map(
      INIT => X"8800",
      LOC => "SLICE_X25Y38"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_1_2597,
      ADR1 => UUT_nstate_FFd3_1_2598,
      ADR2 => VCC,
      ADR3 => UUT_nstate_FFd2_1_2599,
      O => UUT_shiftReg_mux0000_0_114
    );
  UUT_nstate_FFd1_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X26Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd1_FXMUX_4754,
      O => UUT_nstate_FFd1_1_DYMUX_8661
    );
  UUT_nstate_FFd1_1_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N65_0,
      O => UUT_nstate_FFd1_1_SRINV_8659
    );
  UUT_nstate_FFd1_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_nstate_FFd1_1_CLKINV_8658
    );
  UUT_nstate_FFd2_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd2_FXMUX_4719,
      O => UUT_nstate_FFd2_1_DYMUX_8673
    );
  UUT_nstate_FFd2_1_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N65_0,
      O => UUT_nstate_FFd2_1_SRINV_8671
    );
  UUT_nstate_FFd2_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_nstate_FFd2_1_CLKINV_8670
    );
  UUT_nstate_FFd3_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd3_FXMUX_5360,
      O => UUT_nstate_FFd3_1_DYMUX_8683
    );
  UUT_nstate_FFd3_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_nstate_FFd3_1_CLKINV_8681
    );
  UUT_nstate_FFd4_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_FXMUX_6797,
      O => UUT_nstate_FFd4_1_DYMUX_8694
    );
  UUT_nstate_FFd4_1_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_In0_0,
      O => UUT_nstate_FFd4_1_SRINV_8692
    );
  UUT_nstate_FFd4_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_nstate_FFd4_1_CLKINV_8691
    );
  N39_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y46",
      PATHPULSE => 798 ps
    )
    port map (
      I => N39,
      O => N39_0
    );
  N39_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y46",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000216_8713,
      O => UUT_out_i2cclk_mux0000216_0
    );
  UUT_out_i2cclk_mux0000216 : X_LUT4
    generic map(
      INIT => X"0A0A",
      LOC => "SLICE_X26Y46"
    )
    port map (
      ADR0 => UUT_out_i2cclk_2445,
      ADR1 => VCC,
      ADR2 => UUT_nstate_FFd2_2446,
      ADR3 => VCC,
      O => UUT_out_i2cclk_mux0000216_8713
    );
  N42_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => N42,
      O => N42_0
    );
  N42_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000_0_0_8737,
      O => UUT_delay_count_mux0000_0_0_0
    );
  UUT_delay_count_mux0000_0_0 : X_LUT4
    generic map(
      INIT => X"F050",
      LOC => "SLICE_X22Y38"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2450,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(0),
      ADR3 => UUT_nstate_FFd1_2447,
      O => UUT_delay_count_mux0000_0_0_8737
    );
  UUT_ClkFallingEdge_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_ClkFallingEdge_DYMUX_8754
    );
  UUT_ClkFallingEdge_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ClkFallingEdge_not0001,
      O => UUT_ClkFallingEdge_SRINV_8752
    );
  UUT_ClkFallingEdge_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ClkFallingEdge_CLKINV_8751
    );
  N126_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => N126,
      O => N126_0
    );
  N126_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => N119,
      O => N119_0
    );
  UUT_N3106_SW0 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X27Y52"
    )
    port map (
      ADR0 => UUT_ack_count(1),
      ADR1 => UUT_ack_count(2),
      ADR2 => UUT_ack_count(0),
      ADR3 => UUT_ack_count(3),
      O => N119
    );
  N157_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y47",
      PATHPULSE => 798 ps
    )
    port map (
      I => N157,
      O => N157_0
    );
  N157_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y47",
      PATHPULSE => 798 ps
    )
    port map (
      I => N43,
      O => N43_0
    );
  UUT_pstate_mux0000_5_SW1 : X_LUT4
    generic map(
      INIT => X"6020",
      LOC => "SLICE_X26Y47"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => UUT_nstate_FFd4_2454,
      ADR2 => UUT_nstate_FFd3_2450,
      ADR3 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      O => N43
    );
  N69_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => N69,
      O => N69_0
    );
  UUT_N3205_SW0 : X_LUT4
    generic map(
      INIT => X"ECEC",
      LOC => "SLICE_X28Y48"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0011,
      ADR1 => UUT_N349_0,
      ADR2 => UUT_N3178_0,
      ADR3 => VCC,
      O => N69
    );
  N78_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => N78,
      O => N78_0
    );
  N78_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => N77,
      O => N77_0
    );
  UUT_shiftReg_mux0000_0_130_SW0 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X26Y31"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_shiftReg(7),
      ADR2 => VCC,
      ADR3 => UUT_shiftReg_mux0000_0_110_0,
      O => N77
    );
  UUT_Madd_counter_addsub0000_cy_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_counter_addsub0000_cy(2),
      O => UUT_Madd_counter_addsub0000_cy_2_0
    );
  UUT_Madd_counter_addsub0000_cy_2_11 : X_LUT4
    generic map(
      INIT => X"8800",
      LOC => "SLICE_X24Y34"
    )
    port map (
      ADR0 => UUT_counter(1),
      ADR1 => UUT_counter(2),
      ADR2 => VCC,
      ADR3 => UUT_counter(0),
      O => UUT_Madd_counter_addsub0000_cy(2)
    );
  UUT_N67_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N67,
      O => UUT_N67_0
    );
  UUT_Mtridata_in_i2c_not00011222 : X_LUT4
    generic map(
      INIT => X"0055",
      LOC => "SLICE_X30Y49"
    )
    port map (
      ADR0 => UUT_ack_count(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_ack_count(4),
      O => UUT_N67
    );
  N105_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => N105,
      O => N105_0
    );
  UUT_shiftReg_mux0000_0_244_SW2 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X24Y32"
    )
    port map (
      ADR0 => UUT_shiftReg_mux0000_0_240_2471,
      ADR1 => UUT_N62_0,
      ADR2 => UUT_shiftReg(0),
      ADR3 => UUT_shiftReg(2),
      O => N105
    );
  CLK_clk_div_7_rt : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X33Y35"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => CLK_clk_div(7),
      ADR3 => VCC,
      O => CLK_clk_div_7_rt_4328
    );
  UUT_delay_count_4_rt_1 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X21Y35"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(4),
      ADR3 => VCC,
      O => UUT_delay_count_4_rt
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_3_Q : X_LUT4
    generic map(
      INIT => X"A0A0",
      LOC => "SLICE_X21Y36"
    )
    port map (
      ADR0 => UUT_delay_count(6),
      ADR1 => VCC,
      ADR2 => UUT_delay_count(7),
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(3)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_5_1 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X21Y37"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(9),
      ADR2 => VCC,
      ADR3 => UUT_delay_count(10),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut_5_1_4423
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_7_INV_0 : X_LUT4
    generic map(
      INIT => X"00FF",
      LOC => "SLICE_X21Y38"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(15),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(7)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_1_Q : X_LUT4
    generic map(
      INIT => X"AA00",
      LOC => "SLICE_X21Y32"
    )
    port map (
      ADR0 => UUT_delay_count(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(6),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(1)
    );
  UUT_delay_count_8_rt_2 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X21Y33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(8),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_G
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_5_Q : X_LUT4
    generic map(
      INIT => X"0005",
      LOC => "SLICE_X21Y34"
    )
    port map (
      ADR0 => UUT_delay_count(14),
      ADR1 => VCC,
      ADR2 => UUT_delay_count(13),
      ADR3 => UUT_delay_count(15),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(5)
    );
  UUT_Mtridata_in_i2c_not000181_F : X_LUT4
    generic map(
      INIT => X"0099",
      LOC => "SLICE_X27Y46"
    )
    port map (
      ADR0 => UUT_ack_count(1),
      ADR1 => UUT_nstate_FFd2_2446,
      ADR2 => VCC,
      ADR3 => UUT_ack_count(4),
      O => N189
    );
  UUT_nstate_FFd4_In37_F : X_LUT4
    generic map(
      INIT => X"0B0A",
      LOC => "SLICE_X24Y42"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2454,
      ADR1 => CLK_sI2C_Clk_2469,
      ADR2 => UUT_nstate_FFd2_2446,
      ADR3 => SW_3_IBUF_2443,
      O => N195
    );
  UUT_shiftReg_mux0000_0_244_SW1_F : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X24Y30"
    )
    port map (
      ADR0 => UUT_shiftReg(4),
      ADR1 => UUT_N26_0,
      ADR2 => UUT_shiftReg(6),
      ADR3 => UUT_N62_0,
      O => N138
    );
  UUT_shiftReg_mux0000_0_244_SW3_F : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X25Y33"
    )
    port map (
      ADR0 => UUT_N62_0,
      ADR1 => UUT_shiftReg(2),
      ADR2 => UUT_N26_0,
      ADR3 => UUT_shiftReg(0),
      O => N140
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_3_1 : X_LUT4
    generic map(
      INIT => X"0303",
      LOC => "SLICE_X29Y53"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(10),
      ADR2 => UUT_ack_count(11),
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0000_lut_3_1_3634
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_1_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X35Y5"
    )
    port map (
      ADR0 => UUT_writeCount(6),
      ADR1 => UUT_writeCount(12),
      ADR2 => UUT_writeCount(11),
      ADR3 => UUT_writeCount(10),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(1)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_3_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X35Y6"
    )
    port map (
      ADR0 => UUT_writeCount(17),
      ADR1 => UUT_writeCount(16),
      ADR2 => UUT_writeCount(18),
      ADR3 => UUT_writeCount(4),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(3)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_5_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X35Y7"
    )
    port map (
      ADR0 => UUT_writeCount(24),
      ADR1 => UUT_writeCount(23),
      ADR2 => UUT_writeCount(22),
      ADR3 => UUT_writeCount(2),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(5)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_7_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X35Y8"
    )
    port map (
      ADR0 => UUT_writeCount(30),
      ADR1 => UUT_writeCount(0),
      ADR2 => UUT_writeCount(28),
      ADR3 => UUT_writeCount(29),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(7)
    );
  UUT_delay_count_15_rt : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X21Y27"
    )
    port map (
      ADR0 => UUT_delay_count(15),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_15_rt_4051
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_1_Q : X_LUT4
    generic map(
      INIT => X"C0C0",
      LOC => "SLICE_X31Y50"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(3),
      ADR2 => UUT_ack_count(2),
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(1)
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_3_Q : X_LUT4
    generic map(
      INIT => X"8080",
      LOC => "SLICE_X31Y51"
    )
    port map (
      ADR0 => UUT_ack_count(6),
      ADR1 => UUT_ack_count(5),
      ADR2 => UUT_ack_count(7),
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(3)
    );
  UUT_nstate_cmp_eq0001_SW1 : X_LUT4
    generic map(
      INIT => X"FDFF",
      LOC => "SLICE_X31Y52"
    )
    port map (
      ADR0 => UUT_ack_count(0),
      ADR1 => UUT_ack_count(10),
      ADR2 => UUT_ack_count(11),
      ADR3 => UUT_ack_count(8),
      O => N91
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_1_Q : X_LUT4
    generic map(
      INIT => X"000F",
      LOC => "SLICE_X19Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(3),
      ADR3 => UUT_delay_count(4),
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_1_Q_3275
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_3_INV_0 : X_LUT4
    generic map(
      INIT => X"00FF",
      LOC => "SLICE_X19Y26"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(7),
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_3_Q
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_5_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X19Y27"
    )
    port map (
      ADR0 => UUT_delay_count(10),
      ADR1 => UUT_delay_count(9),
      ADR2 => UUT_delay_count(11),
      ADR3 => UUT_delay_count(12),
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_5_Q_3338
    );
  UUT_ack_count_11_rt : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X37Y64"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_ack_count(11),
      O => UUT_ack_count_11_rt_3577
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_1_1 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X29Y52"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(5),
      ADR2 => VCC,
      ADR3 => UUT_ack_count(4),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut_1_1_3604
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_2_INV_0 : X_LUT4
    generic map(
      INIT => X"5555",
      LOC => "SLICE_X31Y51"
    )
    port map (
      ADR0 => UUT_ack_count(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(2)
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_4_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X31Y52"
    )
    port map (
      ADR0 => UUT_ack_count(10),
      ADR1 => UUT_ack_count(9),
      ADR2 => UUT_ack_count(11),
      ADR3 => UUT_ack_count(8),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(4)
    );
  CLK_Mcount_clk_div_lut_0_INV_0 : X_LUT4
    generic map(
      INIT => X"3333",
      LOC => "SLICE_X33Y32"
    )
    port map (
      ADR0 => VCC,
      ADR1 => CLK_clk_div(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => CLK_Mcount_clk_div_lut(0)
    );
  CLK_clk_div_0 : X_SFF
    generic map(
      LOC => "SLICE_X33Y32",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_0_DXMUX_4203,
      CE => VCC,
      CLK => CLK_clk_div_0_CLKINV_4166,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_0_SRINV_4167,
      O => CLK_clk_div(0)
    );
  CLK_clk_div_3 : X_SFF
    generic map(
      LOC => "SLICE_X33Y33",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_2_DYMUX_4238,
      CE => VCC,
      CLK => CLK_clk_div_2_CLKINV_4216,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_2_SRINV_4217,
      O => CLK_clk_div(3)
    );
  CLK_clk_div_1 : X_SFF
    generic map(
      LOC => "SLICE_X33Y32",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_0_DYMUX_4183,
      CE => VCC,
      CLK => CLK_clk_div_0_CLKINV_4166,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_0_SRINV_4167,
      O => CLK_clk_div(1)
    );
  CLK_clk_div_7 : X_SFF
    generic map(
      LOC => "SLICE_X33Y35",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_6_DYMUX_4333,
      CE => VCC,
      CLK => CLK_clk_div_6_CLKINV_4319,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_6_SRINV_4320,
      O => CLK_clk_div(7)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_0_Q : X_LUT4
    generic map(
      INIT => X"0005",
      LOC => "SLICE_X35Y5"
    )
    port map (
      ADR0 => UUT_writeCount(9),
      ADR1 => VCC,
      ADR2 => UUT_writeCount(7),
      ADR3 => UUT_writeCount(8),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(0)
    );
  UUT_counter_mux0000_4_24_SW0 : X_LUT4
    generic map(
      INIT => X"FEFF",
      LOC => "SLICE_X26Y35"
    )
    port map (
      ADR0 => UUT_counter(1),
      ADR1 => UUT_counter(3),
      ADR2 => UUT_counter(2),
      ADR3 => UUT_counter(4),
      O => N169_pack_1
    );
  UUT_Madd_writeCount_share0000_lut_0_INV_0 : X_LUT4
    generic map(
      INIT => X"3333",
      LOC => "SLICE_X37Y0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Madd_writeCount_share0000_lut(0)
    );
  UUT_shiftReg_mux0000_1_SW0 : X_LUT4
    generic map(
      INIT => X"ABA8",
      LOC => "SLICE_X25Y32"
    )
    port map (
      ADR0 => N106,
      ADR1 => UUT_shiftReg_mux0000_0_25_0,
      ADR2 => UUT_shiftReg_mux0000_0_216_0,
      ADR3 => N105_0,
      O => UUT_shiftReg_mux0000_1_SW0_O_pack_1
    );
  UUT_shiftReg_mux0000_5_SW0 : X_LUT4
    generic map(
      INIT => X"FE10",
      LOC => "SLICE_X25Y31"
    )
    port map (
      ADR0 => UUT_shiftReg_mux0000_0_25_0,
      ADR1 => UUT_shiftReg_mux0000_0_216_0,
      ADR2 => N102_0,
      ADR3 => N103,
      O => UUT_shiftReg_mux0000_5_SW0_O_pack_1
    );
  UUT_shiftReg_mux0000_0_119 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X25Y30"
    )
    port map (
      ADR0 => UUT_N13_0,
      ADR1 => UUT_shiftReg_mux0000_0_114_0,
      ADR2 => UUT_N31_0,
      ADR3 => UUT_N26_0,
      O => UUT_shiftReg_mux0000_0_119_O_pack_1
    );
  UUT_out_i2cclk_mux0000204 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X28Y51"
    )
    port map (
      ADR0 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1,
      ADR1 => UUT_ack_count_cmp_eq0003,
      ADR2 => UUT_ack_count_and0025,
      ADR3 => UUT_out_i2cclk_mux0000176_0,
      O => UUT_out_i2cclk_mux0000204_O_pack_1
    );
  UUT_nstate_FFd4_In77 : X_LUT4
    generic map(
      INIT => X"A300",
      LOC => "SLICE_X25Y41"
    )
    port map (
      ADR0 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      ADR1 => UUT_nstate_cmp_eq0001_0,
      ADR2 => UUT_nstate_FFd3_2450,
      ADR3 => UUT_nstate_FFd4_2454,
      O => UUT_nstate_FFd4_In77_O_pack_1
    );
  UUT_shiftReg_mux0000_0_2311 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X22Y35"
    )
    port map (
      ADR0 => UUT_N0_0,
      ADR1 => UUT_N12,
      ADR2 => UUT_shiftReg(0),
      ADR3 => UUT_shiftReg(1),
      O => UUT_shiftReg_mux0000_0_231
    );
  UUT_shiftReg_mux0000_2_111 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X26Y32"
    )
    port map (
      ADR0 => UUT_N0_0,
      ADR1 => UUT_N12,
      ADR2 => UUT_shiftReg(2),
      ADR3 => UUT_shiftReg(3),
      O => UUT_shiftReg_mux0000_2_11
    );
  UUT_shiftReg_mux0000_3_231 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X26Y33"
    )
    port map (
      ADR0 => UUT_shiftReg(4),
      ADR1 => UUT_N12,
      ADR2 => UUT_N0_0,
      ADR3 => UUT_shiftReg(3),
      O => UUT_shiftReg_mux0000_3_23
    );
  UUT_shiftReg_mux0000_4_111 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X27Y32"
    )
    port map (
      ADR0 => UUT_N12,
      ADR1 => UUT_N0_0,
      ADR2 => UUT_shiftReg(5),
      ADR3 => UUT_shiftReg(4),
      O => UUT_shiftReg_mux0000_4_11
    );
  UUT_ClkRisingEdge_and000011 : X_LUT4
    generic map(
      INIT => X"F000",
      LOC => "SLICE_X26Y30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_ClkEdge(1),
      ADR3 => UUT_ClkEdge(0),
      O => UUT_ClkRisingEdge_and00001
    );
  UUT_delay_count_mux0000_0_251 : X_LUT4
    generic map(
      INIT => X"AA00",
      LOC => "SLICE_X20Y23"
    )
    port map (
      ADR0 => UUT_delay_count_share0000(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_N4_0,
      O => UUT_delay_count_mux0000_0_25
    );
  UUT_Dir_mux0000194_SW1 : X_LUT4
    generic map(
      INIT => X"FEEE",
      LOC => "SLICE_X25Y44"
    )
    port map (
      ADR0 => UUT_Dir_mux0000121_0,
      ADR1 => N134_0,
      ADR2 => UUT_N27,
      ADR3 => UUT_delay_count_or0000,
      O => UUT_Dir_mux0000194_SW1_O_pack_1
    );
  UUT_ack_count_mux0000_0_43 : X_LUT4
    generic map(
      INIT => X"8880",
      LOC => "SLICE_X29Y51"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0006_0,
      ADR1 => UUT_Mtridata_in_i2c_cmp_eq0000,
      ADR2 => UUT_ack_count(0),
      ADR3 => UUT_ClkRisingEdge_2465,
      O => UUT_ack_count_mux0000_0_43_O_pack_1
    );
  UUT_Mtrien_in_i2c_mux00009 : X_LUT4
    generic map(
      INIT => X"4000",
      LOC => "SLICE_X26Y41"
    )
    port map (
      ADR0 => UUT_ClkFallingEdge_2566,
      ADR1 => UUT_N31_0,
      ADR2 => UUT_Mtridata_in_i2c_mux0000119_0,
      ADR3 => UUT_Mtrien_in_i2c_2614,
      O => UUT_Mtrien_in_i2c_mux00009_O_pack_1
    );
  I2C_Data_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD18",
      PATHPULSE => 798 ps
    )
    port map (
      I => I2C_Data_INBUF,
      O => UUT_out_i2c
    );
  UUT_Mtridata_in_i2c_not000181_G : X_LUT4
    generic map(
      INIT => X"0100",
      LOC => "SLICE_X27Y46"
    )
    port map (
      ADR0 => UUT_ack_count(1),
      ADR1 => UUT_nstate_FFd2_2446,
      ADR2 => UUT_nstate_FFd1_2447,
      ADR3 => UUT_ack_count(4),
      O => N190
    );
  UUT_writeCount_mux0000_0_G : X_LUT4
    generic map(
      INIT => X"FA3A",
      LOC => "SLICE_X29Y16"
    )
    port map (
      ADR0 => UUT_writeCount(0),
      ADR1 => UUT_N13_0,
      ADR2 => UUT_nstate_FFd3_2450,
      ADR3 => N25_0,
      O => N198
    );
  UUT_counter_mux0000_0_G : X_LUT4
    generic map(
      INIT => X"F7F0",
      LOC => "SLICE_X26Y34"
    )
    port map (
      ADR0 => UUT_Madd_counter_addsub0000_cy_2_0,
      ADR1 => UUT_counter(3),
      ADR2 => UUT_N112_0,
      ADR3 => UUT_nstate_FFd2_2446,
      O => N192
    );
  UUT_counter_mux0000_1_G : X_LUT4
    generic map(
      INIT => X"ACA0",
      LOC => "SLICE_X27Y35"
    )
    port map (
      ADR0 => UUT_N112_0,
      ADR1 => UUT_ClkRisingEdge_2465,
      ADR2 => UUT_counter(3),
      ADR3 => UUT_nstate_cmp_eq0010,
      O => N186
    );
  UUT_counter_mux0000_2_G : X_LUT4
    generic map(
      INIT => X"CEEE",
      LOC => "SLICE_X25Y34"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => UUT_N112_0,
      ADR2 => UUT_counter(0),
      ADR3 => UUT_counter(1),
      O => N194
    );
  UUT_counter_mux0000_3_G : X_LUT4
    generic map(
      INIT => X"CECE",
      LOC => "SLICE_X25Y35"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => UUT_N112_0,
      ADR2 => UUT_counter(0),
      ADR3 => VCC,
      O => N188
    );
  UUT_nstate_FFd4_In37_G : X_LUT4
    generic map(
      INIT => X"0004",
      LOC => "SLICE_X24Y42"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2454,
      ADR1 => UUT_pstate(3),
      ADR2 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q,
      ADR3 => UUT_nstate_FFd2_2446,
      O => N196
    );
  UUT_shiftReg_mux0000_0_244_SW1_G : X_LUT4
    generic map(
      INIT => X"FF80",
      LOC => "SLICE_X24Y30"
    )
    port map (
      ADR0 => UUT_shiftReg(4),
      ADR1 => UUT_ClkRisingEdge_2465,
      ADR2 => UUT_nstate_cmp_eq0010,
      ADR3 => UUT_shiftReg(6),
      O => N139
    );
  UUT_shiftReg_mux0000_0_244_SW3_G : X_LUT4
    generic map(
      INIT => X"EAAA",
      LOC => "SLICE_X25Y33"
    )
    port map (
      ADR0 => UUT_shiftReg(2),
      ADR1 => UUT_nstate_cmp_eq0010,
      ADR2 => UUT_ClkRisingEdge_2465,
      ADR3 => UUT_shiftReg(0),
      O => N141
    );
  UUT_Madd_ack_count_share0000_lut_0_INV_0 : X_LUT4
    generic map(
      INIT => X"0F0F",
      LOC => "SLICE_X37Y59"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_ack_count(0),
      ADR3 => VCC,
      O => UUT_Madd_ack_count_share0000_lut(0)
    );
  UUT_ack_count_0 : X_SFF
    generic map(
      LOC => "SLICE_X29Y51",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_0_DXMUX_5894,
      CE => VCC,
      CLK => UUT_ack_count_0_CLKINV_5878,
      SET => GND,
      RST => GND,
      SSET => UUT_ack_count_0_SRINV_5879,
      SRST => GND,
      O => UUT_ack_count(0)
    );
  UUT_Dir_mux00012 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X23Y34"
    )
    port map (
      ADR0 => UUT_delay_count(4),
      ADR1 => UUT_delay_count(6),
      ADR2 => UUT_Dir_mux00012_SW0_O,
      ADR3 => UUT_delay_count(7),
      O => UUT_shiftReg_cmp_eq0002
    );
  UUT_ack_count_mux0000_10_218 : X_LUT4
    generic map(
      INIT => X"33BF",
      LOC => "SLICE_X30Y51"
    )
    port map (
      ADR0 => UUT_ack_count_mux0000_10_23_0,
      ADR1 => UUT_N32_0,
      ADR2 => UUT_ack_count_mux0000_10_25_SW0_O,
      ADR3 => UUT_ClkRisingEdge_2465,
      O => UUT_N14
    );
  UUT_N320 : X_LUT4
    generic map(
      INIT => X"CE4E",
      LOC => "SLICE_X30Y48"
    )
    port map (
      ADR0 => UUT_ack_count(5),
      ADR1 => UUT_ack_count(6),
      ADR2 => UUT_ack_count(4),
      ADR3 => UUT_N33_O,
      O => UUT_N320_5968
    );
  UUT_N349 : X_LUT4
    generic map(
      INIT => X"CC8C",
      LOC => "SLICE_X28Y49"
    )
    port map (
      ADR0 => UUT_N327_0,
      ADR1 => UUT_nstate_FFd1_2447,
      ADR2 => UUT_ack_count_and0025,
      ADR3 => UUT_N320_0,
      O => UUT_N349_5992
    );
  UUT_N621 : X_LUT4
    generic map(
      INIT => X"A0A0",
      LOC => "SLICE_X24Y39"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2465,
      ADR1 => VCC,
      ADR2 => UUT_nstate_cmp_eq0010,
      ADR3 => VCC,
      O => UUT_N62
    );
  UUT_N392 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X30Y56"
    )
    port map (
      ADR0 => UUT_ack_count(10),
      ADR1 => UUT_ack_count(11),
      ADR2 => UUT_ack_count(9),
      ADR3 => UUT_N392_SW0_O,
      O => UUT_N392_6040
    );
  UUT_shiftReg_or000017 : X_LUT4
    generic map(
      INIT => X"F7FF",
      LOC => "SLICE_X18Y27"
    )
    port map (
      ADR0 => UUT_delay_count(9),
      ADR1 => UUT_delay_count(4),
      ADR2 => UUT_shiftReg_or000012_O,
      ADR3 => UUT_delay_count(1),
      O => UUT_shiftReg_or000017_6064
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_0_INV_0 : X_LUT4
    generic map(
      INIT => X"0F0F",
      LOC => "SLICE_X31Y50"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_ack_count(1),
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(0)
    );
  UUT_delay_count_2_rt : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X19Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(2),
      O => UUT_delay_count_2_rt_3288
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_2_Q : X_LUT4
    generic map(
      INIT => X"8888",
      LOC => "SLICE_X19Y26"
    )
    port map (
      ADR0 => UUT_delay_count(5),
      ADR1 => UUT_delay_count(6),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_2_Q_3322
    );
  UUT_delay_count_8_rt : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X19Y27"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(8),
      ADR3 => VCC,
      O => UUT_delay_count_8_rt_3352
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_0_1 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X29Y52"
    )
    port map (
      ADR0 => UUT_ack_count(1),
      ADR1 => UUT_ack_count(2),
      ADR2 => UUT_ack_count(3),
      ADR3 => UUT_ack_count(0),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut_0_1_3617
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_2_1 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X29Y53"
    )
    port map (
      ADR0 => UUT_ack_count(6),
      ADR1 => UUT_ack_count(8),
      ADR2 => UUT_ack_count(7),
      ADR3 => UUT_ack_count(9),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut_2_1_3650
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_2_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X35Y6"
    )
    port map (
      ADR0 => UUT_writeCount(5),
      ADR1 => UUT_writeCount(15),
      ADR2 => UUT_writeCount(14),
      ADR3 => UUT_writeCount(13),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(2)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_4_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X35Y7"
    )
    port map (
      ADR0 => UUT_writeCount(21),
      ADR1 => UUT_writeCount(3),
      ADR2 => UUT_writeCount(19),
      ADR3 => UUT_writeCount(20),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(4)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_6_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X35Y8"
    )
    port map (
      ADR0 => UUT_writeCount(1),
      ADR1 => UUT_writeCount(27),
      ADR2 => UUT_writeCount(25),
      ADR3 => UUT_writeCount(26),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(6)
    );
  UUT_Madd_delay_count_share0000_lut_0_INV_0 : X_LUT4
    generic map(
      INIT => X"0F0F",
      LOC => "SLICE_X21Y20"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(0),
      ADR3 => VCC,
      O => UUT_Madd_delay_count_share0000_lut(0)
    );
  UUT_writeCount_0 : X_FF
    generic map(
      LOC => "SLICE_X29Y16",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_0_DXMUX_4686,
      CE => VCC,
      CLK => UUT_writeCount_0_CLKINV_4669,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(0)
    );
  UUT_nstate_FFd2_In1_G : X_LUT4
    generic map(
      INIT => X"A0A3",
      LOC => "SLICE_X25Y39"
    )
    port map (
      ADR0 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      ADR1 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q,
      ADR2 => UUT_nstate_FFd2_2446,
      ADR3 => UUT_nstate_FFd4_2454,
      O => N143
    );
  UUT_nstate_FFd2 : X_SFF
    generic map(
      LOC => "SLICE_X25Y39",
      INIT => '0'
    )
    port map (
      I => UUT_nstate_FFd2_DXMUX_4720,
      CE => VCC,
      CLK => UUT_nstate_FFd2_CLKINV_4702,
      SET => GND,
      RST => GND,
      SSET => UUT_nstate_FFd2_SRINV_4703,
      SRST => GND,
      O => UUT_nstate_FFd2_2446
    );
  UUT_nstate_FFd1_In271_G : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X27Y40"
    )
    port map (
      ADR0 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q,
      ADR1 => UUT_pstate(3),
      ADR2 => UUT_pstate(2),
      ADR3 => UUT_N32_0,
      O => N200
    );
  UUT_nstate_FFd1 : X_SFF
    generic map(
      LOC => "SLICE_X27Y40",
      INIT => '0'
    )
    port map (
      I => UUT_nstate_FFd1_DXMUX_4755,
      CE => VCC,
      CLK => UUT_nstate_FFd1_CLKINV_4737,
      SET => GND,
      RST => GND,
      SSET => UUT_nstate_FFd1_SRINV_4738,
      SRST => GND,
      O => UUT_nstate_FFd1_2447
    );
  UUT_counter_4 : X_FF
    generic map(
      LOC => "SLICE_X26Y34",
      INIT => '0'
    )
    port map (
      I => UUT_counter_4_DXMUX_4787,
      CE => VCC,
      CLK => UUT_counter_4_CLKINV_4771,
      SET => GND,
      RST => GND,
      O => UUT_counter(4)
    );
  UUT_counter_3 : X_FF
    generic map(
      LOC => "SLICE_X27Y35",
      INIT => '0'
    )
    port map (
      I => UUT_counter_3_DXMUX_4818,
      CE => VCC,
      CLK => UUT_counter_3_CLKINV_4801,
      SET => GND,
      RST => GND,
      O => UUT_counter(3)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_4_1_INV_0 : X_LUT4
    generic map(
      INIT => X"00FF",
      LOC => "SLICE_X21Y37"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(8),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut_4_1
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_6_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X21Y38"
    )
    port map (
      ADR0 => UUT_delay_count(14),
      ADR1 => UUT_delay_count(11),
      ADR2 => UUT_delay_count(13),
      ADR3 => UUT_delay_count(12),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(6)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_0_Q : X_LUT4
    generic map(
      INIT => X"0005",
      LOC => "SLICE_X21Y32"
    )
    port map (
      ADR0 => UUT_delay_count(4),
      ADR1 => VCC,
      ADR2 => UUT_delay_count(2),
      ADR3 => UUT_delay_count(3),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(0)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_2_INV_0 : X_LUT4
    generic map(
      INIT => X"5555",
      LOC => "SLICE_X21Y33"
    )
    port map (
      ADR0 => UUT_delay_count(7),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(2)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_4_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X21Y34"
    )
    port map (
      ADR0 => UUT_delay_count(11),
      ADR1 => UUT_delay_count(10),
      ADR2 => UUT_delay_count(9),
      ADR3 => UUT_delay_count(12),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(4)
    );
  CLK_clk_div_2 : X_SFF
    generic map(
      LOC => "SLICE_X33Y33",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_2_DXMUX_4255,
      CE => VCC,
      CLK => CLK_clk_div_2_CLKINV_4216,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_2_SRINV_4217,
      O => CLK_clk_div(2)
    );
  CLK_clk_div_5 : X_SFF
    generic map(
      LOC => "SLICE_X33Y34",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_4_DYMUX_4290,
      CE => VCC,
      CLK => CLK_clk_div_4_CLKINV_4268,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_4_SRINV_4269,
      O => CLK_clk_div(5)
    );
  CLK_clk_div_4 : X_SFF
    generic map(
      LOC => "SLICE_X33Y34",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_4_DXMUX_4307,
      CE => VCC,
      CLK => CLK_clk_div_4_CLKINV_4268,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_4_SRINV_4269,
      O => CLK_clk_div(4)
    );
  CLK_clk_div_6 : X_SFF
    generic map(
      LOC => "SLICE_X33Y35",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_6_DXMUX_4352,
      CE => VCC,
      CLK => CLK_clk_div_6_CLKINV_4319,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_6_SRINV_4320,
      O => CLK_clk_div(6)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_0_1 : X_LUT4
    generic map(
      INIT => X"0033",
      LOC => "SLICE_X21Y35"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(2),
      ADR2 => VCC,
      ADR3 => UUT_delay_count(3),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut_0_1_4376
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_2_1_INV_0 : X_LUT4
    generic map(
      INIT => X"5555",
      LOC => "SLICE_X21Y36"
    )
    port map (
      ADR0 => UUT_delay_count(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0002_lut_2_1
    );
  UUT_counter_2 : X_FF
    generic map(
      LOC => "SLICE_X25Y34",
      INIT => '0'
    )
    port map (
      I => UUT_counter_2_DXMUX_4849,
      CE => VCC,
      CLK => UUT_counter_2_CLKINV_4833,
      SET => GND,
      RST => GND,
      O => UUT_counter(2)
    );
  UUT_counter_1 : X_FF
    generic map(
      LOC => "SLICE_X25Y35",
      INIT => '0'
    )
    port map (
      I => UUT_counter_1_DXMUX_4880,
      CE => VCC,
      CLK => UUT_counter_1_CLKINV_4862,
      SET => GND,
      RST => GND,
      O => UUT_counter(1)
    );
  UUT_shiftReg_mux0000_7_SW0 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X23Y33"
    )
    port map (
      ADR0 => UUT_N62_0,
      ADR1 => UUT_shiftReg(6),
      ADR2 => UUT_N26_0,
      ADR3 => UUT_Mtridata_in_i2c_mux0000231_O,
      O => N33
    );
  UUT_Dir_mux000011 : X_LUT4
    generic map(
      INIT => X"0002",
      LOC => "SLICE_X28Y46"
    )
    port map (
      ADR0 => UUT_nstate_FFd1_2447,
      ADR1 => UUT_ack_count(7),
      ADR2 => UUT_ack_count(8),
      ADR3 => UUT_Dir_mux000011_SW0_O,
      O => UUT_Dir_mux000011_5004
    );
  UUT_Mtridata_in_i2c_mux000094 : X_LUT4
    generic map(
      INIT => X"EA00",
      LOC => "SLICE_X23Y37"
    )
    port map (
      ADR0 => UUT_Mtridata_in_i2c_mux000078_0,
      ADR1 => UUT_N33_2487,
      ADR2 => UUT_shiftReg(0),
      ADR3 => UUT_Mtridata_in_i2c_mux000091_O,
      O => UUT_Mtridata_in_i2c_mux000094_5028
    );
  UUT_pstate_mux0000_5_115 : X_LUT4
    generic map(
      INIT => X"4F44",
      LOC => "SLICE_X26Y43"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0000_0,
      ADR1 => UUT_nstate_cmp_eq0010,
      ADR2 => UUT_pstate_mux0000_5_115_SW0_O,
      ADR3 => UUT_nstate_FFd1_2447,
      O => UUT_pstate_mux0000_5_115_5052
    );
  UUT_pstate_mux0000_5_1178_SW0_SW0 : X_LUT4
    generic map(
      INIT => X"FEEE",
      LOC => "SLICE_X27Y42"
    )
    port map (
      ADR0 => UUT_pstate_mux0000_5_1175_2496,
      ADR1 => N114_0,
      ADR2 => UUT_pstate_mux0000_5_1129_2498,
      ADR3 => UUT_N69_0,
      O => N98
    );
  UUT_Mtridata_in_i2c_cmp_eq00001 : X_LUT4
    generic map(
      INIT => X"0004",
      LOC => "SLICE_X26Y51"
    )
    port map (
      ADR0 => UUT_N41,
      ADR1 => UUT_N53_0,
      ADR2 => UUT_Mtridata_in_i2c_cmp_eq00001_SW0_O,
      ADR3 => UUT_ack_count(3),
      O => UUT_N50
    );
  UUT_pstate_mux0000_5_Q : X_LUT4
    generic map(
      INIT => X"EEE4",
      LOC => "SLICE_X24Y43"
    )
    port map (
      ADR0 => UUT_pstate(3),
      ADR1 => N42_0,
      ADR2 => UUT_pstate_mux0000_5_1178_SW1_SW0_O,
      ADR3 => UUT_pstate_mux0000_5_115_0,
      O => UUT_pstate_mux0000(5)
    );
  UUT_pstate_3 : X_FF
    generic map(
      LOC => "SLICE_X24Y43",
      INIT => '0'
    )
    port map (
      I => UUT_pstate_3_DXMUX_5129,
      CE => VCC,
      CLK => UUT_pstate_3_CLKINV_5114,
      SET => GND,
      RST => GND,
      O => UUT_pstate(3)
    );
  UUT_Mtridata_in_i2c_mux0000136 : X_LUT4
    generic map(
      INIT => X"FFE0",
      LOC => "SLICE_X27Y41"
    )
    port map (
      ADR0 => UUT_Mtridata_in_i2c_mux000065_0,
      ADR1 => UUT_Mtridata_in_i2c_mux000094_0,
      ADR2 => UUT_Mtridata_in_i2c_mux0000119_0,
      ADR3 => UUT_Mtridata_in_i2c_mux000034_O,
      O => UUT_Mtridata_in_i2c_mux0000
    );
  UUT_Mtridata_in_i2c : X_FF
    generic map(
      LOC => "SLICE_X27Y41",
      INIT => '1'
    )
    port map (
      I => UUT_Mtridata_in_i2c_DXMUX_5161,
      CE => UUT_Mtridata_in_i2c_CEINV_5145,
      CLK => UUT_Mtridata_in_i2c_CLKINV_5146,
      SET => GND,
      RST => GND,
      O => UUT_Mtridata_in_i2c_2515
    );
  UUT_N3205 : X_LUT4
    generic map(
      INIT => X"FFEA",
      LOC => "SLICE_X28Y50"
    )
    port map (
      ADR0 => UUT_N349_0,
      ADR1 => UUT_nstate_cmp_eq0011,
      ADR2 => UUT_N3178_0,
      ADR3 => UUT_N362_2519,
      O => UUT_N3
    );
  UUT_Dir_mux0000121 : X_LUT4
    generic map(
      INIT => X"1F11",
      LOC => "SLICE_X24Y44"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2454,
      ADR1 => UUT_nstate_FFd2_2446,
      ADR2 => UUT_nstate_FFd3_2450,
      ADR3 => UUT_Dir_mux0000108_O,
      O => UUT_Dir_mux0000121_5211
    );
  UUT_N3157 : X_LUT4
    generic map(
      INIT => X"3777",
      LOC => "SLICE_X29Y57"
    )
    port map (
      ADR0 => UUT_ack_count(5),
      ADR1 => UUT_ack_count(7),
      ADR2 => UUT_ack_count(4),
      ADR3 => UUT_N3157_SW0_O,
      O => UUT_N3157_5235
    );
  UUT_N3178 : X_LUT4
    generic map(
      INIT => X"FEFC",
      LOC => "SLICE_X29Y56"
    )
    port map (
      ADR0 => UUT_N3157_0,
      ADR1 => UUT_N392_0,
      ADR2 => UUT_N3106_O,
      ADR3 => UUT_ack_count(8),
      O => UUT_N3178_5259
    );
  UUT_Dir_mux0000611 : X_LUT4
    generic map(
      INIT => X"E0A0",
      LOC => "SLICE_X29Y47"
    )
    port map (
      ADR0 => UUT_Dir_mux000011_0,
      ADR1 => UUT_N60,
      ADR2 => UUT_Dir_mux000058_0,
      ADR3 => UUT_Dir_mux0000611_SW0_O,
      O => UUT_Dir_mux000061
    );
  UUT_Mtrien_in_i2c_mux00002_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X20Y28"
    )
    port map (
      ADR0 => UUT_delay_count(10),
      ADR1 => UUT_Mtrien_in_i2c_mux00002_SW0_SW0_O,
      ADR2 => UUT_delay_count(6),
      ADR3 => UUT_delay_count(4),
      O => N51
    );
  UUT_shiftReg_and00001 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X21Y30"
    )
    port map (
      ADR0 => UUT_delay_count(5),
      ADR1 => UUT_delay_count(8),
      ADR2 => UUT_shiftReg_cmp_eq00031_SW1_O,
      ADR3 => N53,
      O => UUT_shiftReg_and0000
    );
  UUT_nstate_FFd3_In : X_LUT4
    generic map(
      INIT => X"EFE0",
      LOC => "SLICE_X27Y43"
    )
    port map (
      ADR0 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q,
      ADR1 => N13_0,
      ADR2 => UUT_nstate_FFd3_2450,
      ADR3 => UUT_nstate_FFd3_In_SW0_O,
      O => UUT_nstate_FFd3_In_5358
    );
  UUT_nstate_FFd3 : X_FF
    generic map(
      LOC => "SLICE_X27Y43",
      INIT => '0'
    )
    port map (
      I => UUT_nstate_FFd3_DXMUX_5361,
      CE => VCC,
      CLK => UUT_nstate_FFd3_CLKINV_5345,
      SET => GND,
      RST => GND,
      O => UUT_nstate_FFd3_2450
    );
  UUT_Mtrien_in_i2c_mux00002 : X_LUT4
    generic map(
      INIT => X"FF37",
      LOC => "SLICE_X20Y29"
    )
    port map (
      ADR0 => N51_0,
      ADR1 => UUT_shiftReg_and0000_0,
      ADR2 => UUT_shiftReg_cmp_eq0001,
      ADR3 => UUT_shiftReg_or0000,
      O => UUT_N31
    );
  UUT_ack_count_mux0000_0_28 : X_LUT4
    generic map(
      INIT => X"CE0A",
      LOC => "SLICE_X27Y51"
    )
    port map (
      ADR0 => UUT_ack_count(0),
      ADR1 => N153_0,
      ADR2 => UUT_N32_0,
      ADR3 => UUT_ack_count_mux0000_0_18_O,
      O => UUT_ack_count_mux0000_0_28_5410
    );
  UUT_ack_count_mux0000_3_11 : X_LUT4
    generic map(
      INIT => X"7333",
      LOC => "SLICE_X28Y52"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2465,
      ADR1 => UUT_N32_0,
      ADR2 => UUT_nstate_cmp_eq0006_0,
      ADR3 => UUT_Mtridata_in_i2c_cmp_eq0000,
      O => UUT_N211
    );
  UUT_shiftReg_or00002 : X_LUT4
    generic map(
      INIT => X"22EF",
      LOC => "SLICE_X21Y28"
    )
    port map (
      ADR0 => UUT_delay_count(9),
      ADR1 => UUT_delay_count(7),
      ADR2 => UUT_shiftReg_or00002_SW0_O,
      ADR3 => UUT_delay_count(10),
      O => UUT_N331
    );
  UUT_out_i2cclk_mux000026 : X_LUT4
    generic map(
      INIT => X"0008",
      LOC => "SLICE_X30Y52"
    )
    port map (
      ADR0 => UUT_N60,
      ADR1 => UUT_N511,
      ADR2 => UUT_ack_count(9),
      ADR3 => UUT_out_i2cclk_mux000026_SW0_O,
      O => UUT_out_i2cclk_mux000026_5482
    );
  UUT_ack_count_10 : X_FF
    generic map(
      LOC => "SLICE_X36Y64",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_11_DYMUX_7508,
      CE => VCC,
      CLK => UUT_ack_count_11_CLKINV_7500,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(10)
    );
  UUT_ack_count_mux0000_11_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X36Y64"
    )
    port map (
      ADR0 => UUT_ack_count(11),
      ADR1 => UUT_ack_count_share0000(11),
      ADR2 => UUT_N3_0,
      ADR3 => UUT_N14_0,
      O => UUT_ack_count_mux0000(11)
    );
  UUT_ack_count_11 : X_FF
    generic map(
      LOC => "SLICE_X36Y64",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_11_DXMUX_7519,
      CE => VCC,
      CLK => UUT_ack_count_11_CLKINV_7500,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(11)
    );
  UUT_ack_count_1 : X_FF
    generic map(
      LOC => "SLICE_X30Y53",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_1_DYMUX_7540,
      CE => VCC,
      CLK => UUT_ack_count_1_CLKINV_7532,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(1)
    );
  UUT_Mtrien_in_i2c_mux000041 : X_LUT4
    generic map(
      INIT => X"FF0F",
      LOC => "SLICE_X30Y53"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_ack_count(1),
      ADR3 => UUT_ack_count(6),
      O => UUT_Mtrien_in_i2c_mux000041_7550
    );
  UUT_ack_count_2 : X_FF
    generic map(
      LOC => "SLICE_X36Y60",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_3_DYMUX_7572,
      CE => VCC,
      CLK => UUT_ack_count_3_CLKINV_7564,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(2)
    );
  UUT_ack_count_mux0000_3_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X36Y60"
    )
    port map (
      ADR0 => UUT_ack_count(3),
      ADR1 => UUT_ack_count_share0000(3),
      ADR2 => UUT_N211_0,
      ADR3 => UUT_N3_0,
      O => UUT_ack_count_mux0000(3)
    );
  UUT_ack_count_3 : X_FF
    generic map(
      LOC => "SLICE_X36Y60",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_3_DXMUX_7583,
      CE => VCC,
      CLK => UUT_ack_count_3_CLKINV_7564,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(3)
    );
  UUT_ack_count_4 : X_FF
    generic map(
      LOC => "SLICE_X36Y61",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_5_DYMUX_7606,
      CE => VCC,
      CLK => UUT_ack_count_5_CLKINV_7598,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(4)
    );
  UUT_ack_count_mux0000_5_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X36Y61"
    )
    port map (
      ADR0 => UUT_ack_count_share0000(5),
      ADR1 => UUT_ack_count(5),
      ADR2 => UUT_N211_0,
      ADR3 => UUT_N3_0,
      O => UUT_ack_count_mux0000(5)
    );
  UUT_ack_count_5 : X_FF
    generic map(
      LOC => "SLICE_X36Y61",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_5_DXMUX_7617,
      CE => VCC,
      CLK => UUT_ack_count_5_CLKINV_7598,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(5)
    );
  UUT_ack_count_6 : X_FF
    generic map(
      LOC => "SLICE_X36Y62",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_7_DYMUX_7640,
      CE => VCC,
      CLK => UUT_ack_count_7_CLKINV_7632,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(6)
    );
  UUT_ack_count_mux0000_7_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X36Y62"
    )
    port map (
      ADR0 => UUT_ack_count(7),
      ADR1 => UUT_ack_count_share0000(7),
      ADR2 => UUT_N3_0,
      ADR3 => UUT_N14_0,
      O => UUT_ack_count_mux0000(7)
    );
  UUT_ack_count_7 : X_FF
    generic map(
      LOC => "SLICE_X36Y62",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_7_DXMUX_7651,
      CE => VCC,
      CLK => UUT_ack_count_7_CLKINV_7632,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(7)
    );
  UUT_ack_count_8 : X_FF
    generic map(
      LOC => "SLICE_X36Y63",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_9_DYMUX_7674,
      CE => VCC,
      CLK => UUT_ack_count_9_CLKINV_7666,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(8)
    );
  UUT_ack_count_mux0000_9_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X36Y63"
    )
    port map (
      ADR0 => UUT_ack_count_share0000(9),
      ADR1 => UUT_N14_0,
      ADR2 => UUT_ack_count(9),
      ADR3 => UUT_N3_0,
      O => UUT_ack_count_mux0000(9)
    );
  UUT_ack_count_9 : X_FF
    generic map(
      LOC => "SLICE_X36Y63",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_9_DXMUX_7685,
      CE => VCC,
      CLK => UUT_ack_count_9_CLKINV_7666,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(9)
    );
  UUT_writeCount_10 : X_FF
    generic map(
      LOC => "SLICE_X36Y4",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_11_DYMUX_7708,
      CE => VCC,
      CLK => UUT_writeCount_11_CLKINV_7700,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(10)
    );
  UUT_writeCount_mux0000_11_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X36Y4"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(11),
      ADR1 => UUT_N11,
      ADR2 => UUT_N35,
      ADR3 => UUT_writeCount(11),
      O => UUT_writeCount_mux0000(11)
    );
  UUT_shiftReg_mux0000_0_110 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X24Y31"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0012_0,
      ADR1 => UUT_nstate_FFd1_2447,
      ADR2 => UUT_shiftReg_mux0000_0_131_O,
      ADR3 => UUT_N69_0,
      O => UUT_shiftReg_mux0000_0_110_6088
    );
  UUT_shiftReg_mux0000_0_111 : X_LUT4
    generic map(
      INIT => X"DFFF",
      LOC => "SLICE_X22Y28"
    )
    port map (
      ADR0 => UUT_N45,
      ADR1 => N71_0,
      ADR2 => UUT_shiftReg_cmp_eq0001,
      ADR3 => UUT_N38_0,
      O => UUT_N13
    );
  UUT_shiftReg_mux0000_0_130 : X_LUT4
    generic map(
      INIT => X"FEF4",
      LOC => "SLICE_X24Y28"
    )
    port map (
      ADR0 => UUT_N31_0,
      ADR1 => N86_0,
      ADR2 => UUT_shiftReg_mux0000_0_110_0,
      ADR3 => UUT_shiftReg_mux0000_0_119_SW1_O,
      O => UUT_N0
    );
  UUT_shiftReg_mux0000_0_216 : X_LUT4
    generic map(
      INIT => X"0400",
      LOC => "SLICE_X23Y31"
    )
    port map (
      ADR0 => UUT_delay_count(1),
      ADR1 => UUT_N45,
      ADR2 => UUT_delay_count(0),
      ADR3 => UUT_N33_2487,
      O => UUT_shiftReg_mux0000_0_216_6160
    );
  UUT_Mtrien_in_i2c_mux0000141 : X_LUT4
    generic map(
      INIT => X"FF32",
      LOC => "SLICE_X26Y41"
    )
    port map (
      ADR0 => UUT_Mtrien_in_i2c_mux000061_0,
      ADR1 => UUT_nstate_cmp_eq0006_0,
      ADR2 => UUT_Mtrien_in_i2c_mux00009_O,
      ADR3 => UUT_Mtrien_in_i2c_mux0000133_0,
      O => UUT_Mtrien_in_i2c_mux0000
    );
  UUT_Mtrien_in_i2c : X_FF
    generic map(
      LOC => "SLICE_X26Y41",
      INIT => '0'
    )
    port map (
      I => UUT_Mtrien_in_i2c_DXMUX_6191,
      CE => UUT_Mtrien_in_i2c_CEINV_6175,
      CLK => UUT_Mtrien_in_i2c_CLKINV_6176,
      SET => GND,
      RST => GND,
      O => UUT_Mtrien_in_i2c_2614
    );
  UUT_Mtrien_in_i2c_mux0000133 : X_LUT4
    generic map(
      INIT => X"00A2",
      LOC => "SLICE_X28Y47"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0006_0,
      ADR1 => UUT_ack_count_and0025,
      ADR2 => UUT_Mtrien_in_i2c_mux0000113_O,
      ADR3 => UUT_Mtridata_in_i2c_cmp_eq0000,
      O => UUT_Mtrien_in_i2c_mux0000133_6217
    );
  UUT_out_i2cclk_mux0000104 : X_LUT4
    generic map(
      INIT => X"FFA8",
      LOC => "SLICE_X29Y50"
    )
    port map (
      ADR0 => CLK_sI2C_Clk_2469,
      ADR1 => UUT_out_i2cclk_mux000066_0,
      ADR2 => UUT_out_i2cclk_mux000053_O,
      ADR3 => UUT_out_i2cclk_mux000097_0,
      O => UUT_out_i2cclk_mux0000104_6241
    );
  UUT_Mtridata_in_i2c_not0001206 : X_LUT4
    generic map(
      INIT => X"F5F4",
      LOC => "SLICE_X27Y49"
    )
    port map (
      ADR0 => UUT_N41,
      ADR1 => UUT_Mtridata_in_i2c_not0001168_0,
      ADR2 => UUT_Mtridata_in_i2c_not00012_0,
      ADR3 => UUT_Mtridata_in_i2c_not0001125_O,
      O => UUT_Mtridata_in_i2c_not0001
    );
  UUT_out_i2cclk_mux0000176 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X29Y55"
    )
    port map (
      ADR0 => UUT_N41,
      ADR1 => UUT_out_i2cclk_mux0000131_0,
      ADR2 => UUT_out_i2cclk_mux0000118_0,
      ADR3 => UUT_out_i2cclk_mux0000163_O,
      O => UUT_out_i2cclk_mux0000176_6289
    );
  UUT_Mtridata_in_i2c_not0001168 : X_LUT4
    generic map(
      INIT => X"0800",
      LOC => "SLICE_X29Y48"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2454,
      ADR1 => UUT_N60,
      ADR2 => UUT_Mtridata_in_i2c_not0001168_SW0_O,
      ADR3 => UUT_N511,
      O => UUT_Mtridata_in_i2c_not0001168_6313
    );
  UUT_writeCount_mux0000_0_SW1 : X_LUT4
    generic map(
      INIT => X"EACA",
      LOC => "SLICE_X28Y16"
    )
    port map (
      ADR0 => UUT_writeCount(0),
      ADR1 => UUT_writeCount_share0000(0),
      ADR2 => UUT_ClkFallingEdge_2566,
      ADR3 => UUT_delay_count_or0000,
      O => N25
    );
  UUT_nstate_cmp_eq0000 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X27Y34"
    )
    port map (
      ADR0 => UUT_counter(4),
      ADR1 => UUT_counter(0),
      ADR2 => UUT_nstate_cmp_eq0000_SW0_O,
      ADR3 => UUT_counter(1),
      O => UUT_nstate_cmp_eq0000_6361
    );
  UUT_nstate_cmp_eq0001 : X_LUT4
    generic map(
      INIT => X"0200",
      LOC => "SLICE_X31Y53"
    )
    port map (
      ADR0 => UUT_N511,
      ADR1 => UUT_ack_count(9),
      ADR2 => N91_0,
      ADR3 => UUT_N60,
      O => UUT_nstate_cmp_eq0001_6385
    );
  UUT_shiftReg_mux0000_6_181 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X24Y33"
    )
    port map (
      ADR0 => UUT_N0_0,
      ADR1 => UUT_shiftReg(7),
      ADR2 => UUT_N12,
      ADR3 => UUT_shiftReg(6),
      O => UUT_shiftReg_mux0000_6_18
    );
  UUT_shiftReg_6 : X_SFF
    generic map(
      LOC => "SLICE_X24Y33",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_6_DXMUX_6416,
      CE => VCC,
      CLK => UUT_shiftReg_6_CLKINV_6400,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_6_SRINV_6401,
      SRST => GND,
      O => UUT_shiftReg(6)
    );
  UUT_shiftReg_mux0000_1_1 : X_LUT4
    generic map(
      INIT => X"FAF0",
      LOC => "SLICE_X25Y32"
    )
    port map (
      ADR0 => UUT_shiftReg(1),
      ADR1 => VCC,
      ADR2 => UUT_shiftReg_mux0000_1_SW0_O,
      ADR3 => UUT_N0_0,
      O => UUT_shiftReg_mux0000_1_1_6446
    );
  UUT_shiftReg_1 : X_SFF
    generic map(
      LOC => "SLICE_X25Y32",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_1_DXMUX_6449,
      CE => VCC,
      CLK => UUT_shiftReg_1_CLKINV_6432,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_1_SRINV_6433,
      SRST => GND,
      O => UUT_shiftReg(1)
    );
  UUT_shiftReg_mux0000_0_8 : X_LUT4
    generic map(
      INIT => X"FF80",
      LOC => "SLICE_X22Y32"
    )
    port map (
      ADR0 => UUT_shiftReg_and0000_0,
      ADR1 => UUT_N26_0,
      ADR2 => UUT_shiftReg_cmp_eq0002_0,
      ADR3 => UUT_shiftReg_mux0000_0_5_O,
      O => UUT_shiftReg_mux0000_0_8_6475
    );
  UUT_Mtridata_in_i2c_not000141 : X_LUT4
    generic map(
      INIT => X"2070",
      LOC => "SLICE_X27Y48"
    )
    port map (
      ADR0 => UUT_ack_count(6),
      ADR1 => N126_0,
      ADR2 => UUT_Mtridata_in_i2c_not000111_O,
      ADR3 => N116_0,
      O => UUT_Mtridata_in_i2c_not000141_5506
    );
  UUT_out_i2cclk_mux000047 : X_LUT4
    generic map(
      INIT => X"8080",
      LOC => "SLICE_X31Y48"
    )
    port map (
      ADR0 => UUT_ack_count(4),
      ADR1 => UUT_ack_count(5),
      ADR2 => UUT_N57,
      ADR3 => VCC,
      O => UUT_out_i2cclk_mux000047_5530
    );
  UUT_out_i2cclk_mux000066 : X_LUT4
    generic map(
      INIT => X"5550",
      LOC => "SLICE_X26Y50"
    )
    port map (
      ADR0 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1,
      ADR1 => VCC,
      ADR2 => UUT_ack_count(1),
      ADR3 => UUT_N27,
      O => UUT_out_i2cclk_mux000066_5554
    );
  UUT_out_i2cclk_mux000097 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X28Y54"
    )
    port map (
      ADR0 => UUT_ack_count(8),
      ADR1 => N181_0,
      ADR2 => N159_0,
      ADR3 => UUT_N41,
      O => UUT_out_i2cclk_mux000097_5578
    );
  UUT_ack_count_mux0000_0_28_SW0 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X27Y45"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2465,
      ADR1 => UUT_ClkFallingEdge_2566,
      ADR2 => UUT_nstate_FFd1_2447,
      ADR3 => UUT_nstate_cmp_eq0011,
      O => N153
    );
  UUT_pstate_mux0000_5_1178_SW0_SW0_SW0 : X_LUT4
    generic map(
      INIT => X"BAB0",
      LOC => "SLICE_X25Y42"
    )
    port map (
      ADR0 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      ADR1 => UUT_nstate_FFd2_2446,
      ADR2 => UUT_N64,
      ADR3 => UUT_nstate_cmp_eq0008,
      O => N114
    );
  UUT_Dir_mux00002241 : X_LUT4
    generic map(
      INIT => X"FEAA",
      LOC => "SLICE_X25Y44"
    )
    port map (
      ADR0 => UUT_Dir_mux000082_0,
      ADR1 => UUT_Dir_mux0000169_0,
      ADR2 => UUT_Dir_mux0000194_SW1_O,
      ADR3 => UUT_Dir_2438,
      O => UUT_Dir_mux0000224
    );
  UUT_Dir : X_SFF
    generic map(
      LOC => "SLICE_X25Y44",
      INIT => '1'
    )
    port map (
      I => UUT_Dir_DXMUX_5657,
      CE => VCC,
      CLK => UUT_Dir_CLKINV_5641,
      SET => GND,
      RST => GND,
      SSET => UUT_Dir_SRINV_5642,
      SRST => GND,
      O => UUT_Dir_2438
    );
  UUT_pstate_mux0000_5_112_SW0 : X_LUT4
    generic map(
      INIT => X"0200",
      LOC => "SLICE_X29Y49"
    )
    port map (
      ADR0 => UUT_N53_0,
      ADR1 => UUT_N41,
      ADR2 => UUT_ack_count(1),
      ADR3 => UUT_N511,
      O => N35
    );
  UUT_pstate_mux0000_5_1138_SW0 : X_LUT4
    generic map(
      INIT => X"FF80",
      LOC => "SLICE_X25Y43"
    )
    port map (
      ADR0 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      ADR1 => UUT_nstate_FFd2_2446,
      ADR2 => UUT_N64,
      ADR3 => UUT_pstate_mux0000_5_1175_2496,
      O => N56
    );
  UUT_ack_count_mux0000_10_23 : X_LUT4
    generic map(
      INIT => X"A000",
      LOC => "SLICE_X30Y50"
    )
    port map (
      ADR0 => UUT_nstate_FFd1_2447,
      ADR1 => VCC,
      ADR2 => UUT_ack_count_and0025,
      ADR3 => UUT_ack_count_cmp_eq0003,
      O => UUT_ack_count_mux0000_10_23_5731
    );
  UUT_shiftReg_mux0000_0_111_SW0_SW1 : X_LUT4
    generic map(
      INIT => X"CE00",
      LOC => "SLICE_X22Y29"
    )
    port map (
      ADR0 => N146_0,
      ADR1 => UUT_ClkFallingEdge_2566,
      ADR2 => N49,
      ADR3 => UUT_shiftReg_mux0000_0_114_0,
      O => N96
    );
  UUT_writeCount_mux0000_8_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X35Y4"
    )
    port map (
      ADR0 => UUT_N11,
      ADR1 => UUT_writeCount_share0000(8),
      ADR2 => UUT_N35,
      ADR3 => UUT_writeCount(8),
      O => UUT_writeCount_mux0000(8)
    );
  UUT_writeCount_8 : X_FF
    generic map(
      LOC => "SLICE_X35Y4",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_8_DXMUX_5784,
      CE => VCC,
      CLK => UUT_writeCount_8_CLKINV_5768,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(8)
    );
  UUT_writeCount_mux0000_9_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X34Y4"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(9),
      ADR1 => UUT_N35,
      ADR2 => UUT_writeCount(9),
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(9)
    );
  UUT_writeCount_9 : X_FF
    generic map(
      LOC => "SLICE_X34Y4",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_9_DXMUX_5814,
      CE => VCC,
      CLK => UUT_writeCount_9_CLKINV_5799,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(9)
    );
  UUT_Mtrien_in_i2c_mux000061 : X_LUT4
    generic map(
      INIT => X"E0A0",
      LOC => "SLICE_X26Y44"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0011,
      ADR1 => UUT_nstate_FFd1_2447,
      ADR2 => UUT_Mtrien_in_i2c_mux000055_0,
      ADR3 => UUT_Mtrien_in_i2c_mux000061_SW0_O,
      O => UUT_Mtrien_in_i2c_mux000061_5839
    );
  UUT_Mtrien_in_i2c_mux000055 : X_LUT4
    generic map(
      INIT => X"0501",
      LOC => "SLICE_X27Y44"
    )
    port map (
      ADR0 => UUT_N64,
      ADR1 => UUT_N50_0,
      ADR2 => UUT_nstate_cmp_eq0008,
      ADR3 => UUT_Mtrien_in_i2c_mux000041_0,
      O => UUT_Mtrien_in_i2c_mux000055_5863
    );
  UUT_ack_count_mux0000_0_601 : X_LUT4
    generic map(
      INIT => X"FFE0",
      LOC => "SLICE_X29Y51"
    )
    port map (
      ADR0 => UUT_N362_2519,
      ADR1 => N69_0,
      ADR2 => UUT_ack_count_share0000(0),
      ADR3 => UUT_ack_count_mux0000_0_43_O,
      O => UUT_ack_count_mux0000_0_60
    );
  UUT_nstate_FFd3_In_SW1 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X26Y42"
    )
    port map (
      ADR0 => UUT_pstate(3),
      ADR1 => UUT_nstate_FFd4_2454,
      ADR2 => UUT_nstate_FFd2_2446,
      ADR3 => UUT_pstate(2),
      O => N13
    );
  UUT_delay_count_0 : X_SFF
    generic map(
      LOC => "SLICE_X20Y23",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_0_DYMUX_7318,
      CE => VCC,
      CLK => UUT_delay_count_0_CLKINV_7307,
      SET => GND,
      RST => GND,
      SSET => UUT_delay_count_0_SRINV_7308,
      SRST => GND,
      O => UUT_delay_count(0)
    );
  UUT_delay_count_1 : X_FF
    generic map(
      LOC => "SLICE_X19Y24",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_1_DYMUX_7341,
      CE => VCC,
      CLK => UUT_delay_count_1_CLKINV_7333,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(1)
    );
  UUT_shiftReg_or000032 : X_LUT4
    generic map(
      INIT => X"00FA",
      LOC => "SLICE_X19Y24"
    )
    port map (
      ADR0 => UUT_delay_count(1),
      ADR1 => VCC,
      ADR2 => UUT_delay_count(0),
      ADR3 => UUT_delay_count(10),
      O => UUT_shiftReg_or000032_7350
    );
  UUT_delay_count_2 : X_FF
    generic map(
      LOC => "SLICE_X20Y21",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_3_DYMUX_7372,
      CE => VCC,
      CLK => UUT_delay_count_3_CLKINV_7364,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(2)
    );
  UUT_delay_count_mux0000_3_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X20Y21"
    )
    port map (
      ADR0 => UUT_N15_0,
      ADR1 => UUT_delay_count(3),
      ADR2 => UUT_delay_count_share0000(3),
      ADR3 => UUT_N4_0,
      O => UUT_delay_count_mux0000(3)
    );
  UUT_delay_count_3 : X_FF
    generic map(
      LOC => "SLICE_X20Y21",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_3_DXMUX_7383,
      CE => VCC,
      CLK => UUT_delay_count_3_CLKINV_7364,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(3)
    );
  UUT_delay_count_4 : X_FF
    generic map(
      LOC => "SLICE_X20Y22",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_5_DYMUX_7406,
      CE => VCC,
      CLK => UUT_delay_count_5_CLKINV_7398,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(4)
    );
  UUT_delay_count_mux0000_5_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X20Y22"
    )
    port map (
      ADR0 => UUT_N15_0,
      ADR1 => UUT_delay_count_share0000(5),
      ADR2 => UUT_delay_count(5),
      ADR3 => UUT_N4_0,
      O => UUT_delay_count_mux0000(5)
    );
  UUT_delay_count_5 : X_FF
    generic map(
      LOC => "SLICE_X20Y22",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_5_DXMUX_7417,
      CE => VCC,
      CLK => UUT_delay_count_5_CLKINV_7398,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(5)
    );
  UUT_delay_count_6 : X_FF
    generic map(
      LOC => "SLICE_X22Y23",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_7_DYMUX_7440,
      CE => VCC,
      CLK => UUT_delay_count_7_CLKINV_7432,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(6)
    );
  UUT_delay_count_mux0000_7_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X22Y23"
    )
    port map (
      ADR0 => UUT_delay_count(7),
      ADR1 => UUT_delay_count_or0000,
      ADR2 => UUT_N4_0,
      ADR3 => UUT_delay_count_share0000(7),
      O => UUT_delay_count_mux0000(7)
    );
  UUT_delay_count_7 : X_FF
    generic map(
      LOC => "SLICE_X22Y23",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_7_DXMUX_7451,
      CE => VCC,
      CLK => UUT_delay_count_7_CLKINV_7432,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(7)
    );
  UUT_delay_count_8 : X_FF
    generic map(
      LOC => "SLICE_X20Y25",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_9_DYMUX_7474,
      CE => VCC,
      CLK => UUT_delay_count_9_CLKINV_7466,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(8)
    );
  UUT_delay_count_mux0000_9_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X20Y25"
    )
    port map (
      ADR0 => UUT_delay_count(9),
      ADR1 => UUT_delay_count_share0000(9),
      ADR2 => UUT_delay_count_or0000,
      ADR3 => UUT_N4_0,
      O => UUT_delay_count_mux0000(9)
    );
  UUT_delay_count_9 : X_FF
    generic map(
      LOC => "SLICE_X20Y25",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_9_DXMUX_7485,
      CE => VCC,
      CLK => UUT_delay_count_9_CLKINV_7466,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(9)
    );
  UUT_shiftReg_mux0000_3_8 : X_LUT4
    generic map(
      INIT => X"ECCC",
      LOC => "SLICE_X23Y32"
    )
    port map (
      ADR0 => UUT_shiftReg_cmp_eq0002_0,
      ADR1 => UUT_shiftReg_mux0000_3_5_O,
      ADR2 => UUT_shiftReg_and0000_0,
      ADR3 => UUT_nstate_cmp_eq0008,
      O => UUT_shiftReg_mux0000_3_8_6499
    );
  UUT_shiftReg_mux0000_5_1 : X_LUT4
    generic map(
      INIT => X"EEAA",
      LOC => "SLICE_X25Y31"
    )
    port map (
      ADR0 => UUT_shiftReg_mux0000_5_SW0_O,
      ADR1 => UUT_shiftReg(5),
      ADR2 => VCC,
      ADR3 => UUT_N0_0,
      O => UUT_shiftReg_mux0000_5_1_6527
    );
  UUT_shiftReg_5 : X_SFF
    generic map(
      LOC => "SLICE_X25Y31",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_5_DXMUX_6530,
      CE => VCC,
      CLK => UUT_shiftReg_5_CLKINV_6513,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_5_SRINV_6514,
      SRST => GND,
      O => UUT_shiftReg(5)
    );
  UUT_shiftReg_mux0000_6_5 : X_LUT4
    generic map(
      INIT => X"F8F0",
      LOC => "SLICE_X22Y33"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0008,
      ADR1 => UUT_shiftReg_and0000_0,
      ADR2 => UUT_shiftReg_mux0000_6_3_O,
      ADR3 => UUT_shiftReg_cmp_eq0002_0,
      O => UUT_shiftReg_mux0000_6_5_6556
    );
  UUT_shiftReg_mux0000_7_1 : X_LUT4
    generic map(
      INIT => X"EFEC",
      LOC => "SLICE_X25Y30"
    )
    port map (
      ADR0 => N78_0,
      ADR1 => N33_0,
      ADR2 => UUT_shiftReg_mux0000_0_119_O,
      ADR3 => N77_0,
      O => UUT_shiftReg_mux0000_7_1_6584
    );
  UUT_shiftReg_7 : X_SFF
    generic map(
      LOC => "SLICE_X25Y30",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_7_DXMUX_6587,
      CE => VCC,
      CLK => UUT_shiftReg_7_CLKINV_6571,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_7_SRINV_6572,
      SRST => GND,
      O => UUT_shiftReg(7)
    );
  UUT_shiftReg_cmp_eq00031 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X21Y29"
    )
    port map (
      ADR0 => UUT_delay_count(15),
      ADR1 => N53,
      ADR2 => UUT_delay_count(3),
      ADR3 => UUT_delay_count(8),
      O => UUT_N38
    );
  UUT_counter_mux0000_4_1 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X24Y36"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2450,
      ADR1 => UUT_nstate_FFd4_2454,
      ADR2 => UUT_nstate_FFd1_2447,
      ADR3 => UUT_counter_mux0000_4_1_SW0_O,
      O => UUT_N112
    );
  UUT_Mtridata_in_i2c_mux000027_SW0 : X_LUT4
    generic map(
      INIT => X"FFF8",
      LOC => "SLICE_X26Y40"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2450,
      ADR1 => UUT_nstate_FFd2_2446,
      ADR2 => UUT_nstate_FFd4_2454,
      ADR3 => UUT_Mtridata_in_i2c_mux000027_SW0_SW0_O,
      O => N128
    );
  UUT_shiftReg_mux0000_0_119_SW0 : X_LUT4
    generic map(
      INIT => X"1B33",
      LOC => "SLICE_X23Y28"
    )
    port map (
      ADR0 => UUT_N38_0,
      ADR1 => N123_0,
      ADR2 => UUT_shiftReg_mux0000_0_111_SW1_O,
      ADR3 => UUT_N45,
      O => N86
    );
  UUT_shiftReg_4 : X_SFF
    generic map(
      LOC => "SLICE_X27Y32",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_4_DYMUX_7080,
      CE => VCC,
      CLK => UUT_shiftReg_4_CLKINV_7071,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_4_SRINV_7072,
      SRST => GND,
      O => UUT_shiftReg(4)
    );
  UUT_writeCount_1 : X_FF
    generic map(
      LOC => "SLICE_X34Y8",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_30_DYMUX_7104,
      CE => VCC,
      CLK => UUT_writeCount_30_CLKINV_7096,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(1)
    );
  UUT_writeCount_mux0000_30_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X34Y8"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(30),
      ADR1 => UUT_N11,
      ADR2 => UUT_N35,
      ADR3 => UUT_writeCount(30),
      O => UUT_writeCount_mux0000(30)
    );
  UUT_writeCount_30 : X_FF
    generic map(
      LOC => "SLICE_X34Y8",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_30_DXMUX_7115,
      CE => VCC,
      CLK => UUT_writeCount_30_CLKINV_7096,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(30)
    );
  UUT_writeCount_2 : X_FF
    generic map(
      LOC => "SLICE_X36Y1",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_3_DYMUX_7138,
      CE => VCC,
      CLK => UUT_writeCount_3_CLKINV_7130,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(2)
    );
  UUT_writeCount_mux0000_3_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X36Y1"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(3),
      ADR1 => UUT_N11,
      ADR2 => UUT_N35,
      ADR3 => UUT_writeCount(3),
      O => UUT_writeCount_mux0000(3)
    );
  UUT_writeCount_3 : X_FF
    generic map(
      LOC => "SLICE_X36Y1",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_3_DXMUX_7149,
      CE => VCC,
      CLK => UUT_writeCount_3_CLKINV_7130,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(3)
    );
  UUT_writeCount_4 : X_FF
    generic map(
      LOC => "SLICE_X36Y3",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_5_DYMUX_7172,
      CE => VCC,
      CLK => UUT_writeCount_5_CLKINV_7164,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(4)
    );
  UUT_writeCount_mux0000_5_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X36Y3"
    )
    port map (
      ADR0 => UUT_writeCount(5),
      ADR1 => UUT_writeCount_share0000(5),
      ADR2 => UUT_N35,
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(5)
    );
  UUT_writeCount_5 : X_FF
    generic map(
      LOC => "SLICE_X36Y3",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_5_DXMUX_7183,
      CE => VCC,
      CLK => UUT_writeCount_5_CLKINV_7164,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(5)
    );
  UUT_writeCount_6 : X_FF
    generic map(
      LOC => "SLICE_X36Y2",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_7_DYMUX_7206,
      CE => VCC,
      CLK => UUT_writeCount_7_CLKINV_7198,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(6)
    );
  UUT_writeCount_mux0000_7_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X36Y2"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(7),
      ADR1 => UUT_N11,
      ADR2 => UUT_N35,
      ADR3 => UUT_writeCount(7),
      O => UUT_writeCount_mux0000(7)
    );
  UUT_writeCount_7 : X_FF
    generic map(
      LOC => "SLICE_X36Y2",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_7_DXMUX_7217,
      CE => VCC,
      CLK => UUT_writeCount_7_CLKINV_7198,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(7)
    );
  UUT_prevClk : X_FF
    generic map(
      LOC => "SLICE_X27Y30",
      INIT => '0'
    )
    port map (
      I => UUT_prevClk_DYMUX_7239,
      CE => VCC,
      CLK => UUT_prevClk_CLKINV_7230,
      SET => GND,
      RST => GND,
      O => UUT_prevClk_2675
    );
  UUT_ClkFallingEdge_not00011 : X_LUT4
    generic map(
      INIT => X"FDFD",
      LOC => "SLICE_X27Y30"
    )
    port map (
      ADR0 => UUT_prevClk_2675,
      ADR1 => UUT_ClkEdge(1),
      ADR2 => UUT_ClkEdge(0),
      ADR3 => VCC,
      O => UUT_ClkFallingEdge_not0001
    );
  UUT_ClkRisingEdge : X_SFF
    generic map(
      LOC => "SLICE_X26Y30",
      INIT => '0'
    )
    port map (
      I => UUT_ClkRisingEdge_DYMUX_7267,
      CE => VCC,
      CLK => UUT_ClkRisingEdge_CLKINV_7256,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => UUT_ClkRisingEdge_SRINV_7257,
      O => UUT_ClkRisingEdge_2465
    );
  UUT_pstate_2 : X_FF
    generic map(
      LOC => "SLICE_X26Y42",
      INIT => '0'
    )
    port map (
      I => UUT_pstate_2_DYMUX_7291,
      CE => VCC,
      CLK => UUT_pstate_2_CLKINV_7283,
      SET => GND,
      RST => GND,
      O => UUT_pstate(2)
    );
  UUT_delay_count_mux0000_11_1 : X_LUT4
    generic map(
      INIT => X"EAFF",
      LOC => "SLICE_X22Y27"
    )
    port map (
      ADR0 => UUT_nstate_FFd1_2447,
      ADR1 => UUT_N45,
      ADR2 => UUT_delay_count_mux0000_11_1_SW1_O,
      ADR3 => UUT_nstate_FFd3_2450,
      O => UUT_N15
    );
  UUT_out_i2cclk_mux00002631 : X_LUT4
    generic map(
      INIT => X"4055",
      LOC => "SLICE_X28Y51"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2450,
      ADR1 => UUT_out_i2cclk_mux0000216_0,
      ADR2 => UUT_out_i2cclk_mux0000204_O,
      ADR3 => UUT_N32_0,
      O => UUT_out_i2cclk_mux0000263
    );
  UUT_out_i2cclk : X_SFF
    generic map(
      LOC => "SLICE_X28Y51",
      INIT => '1'
    )
    port map (
      I => UUT_out_i2cclk_DXMUX_6740,
      CE => VCC,
      CLK => UUT_out_i2cclk_CLKINV_6724,
      SET => GND,
      RST => GND,
      SSET => UUT_out_i2cclk_SRINV_6725,
      SRST => GND,
      O => UUT_out_i2cclk_2445
    );
  UUT_delay_count_mux0000_0_21 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X20Y26"
    )
    port map (
      ADR0 => UUT_delay_count(8),
      ADR1 => N53,
      ADR2 => UUT_delay_count(0),
      ADR3 => UUT_shiftReg_cmp_eq00031_SW2_O,
      O => UUT_delay_count_and0000
    );
  UUT_nstate_FFd4_In791 : X_LUT4
    generic map(
      INIT => X"FFAA",
      LOC => "SLICE_X25Y41"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_In37,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_nstate_FFd4_In77_O,
      O => UUT_nstate_FFd4_In79
    );
  UUT_nstate_FFd4 : X_SFF
    generic map(
      LOC => "SLICE_X25Y41",
      INIT => '0'
    )
    port map (
      I => UUT_nstate_FFd4_DXMUX_6798,
      CE => VCC,
      CLK => UUT_nstate_FFd4_CLKINV_6780,
      SET => GND,
      RST => GND,
      SSET => UUT_nstate_FFd4_SRINV_6781,
      SRST => GND,
      O => UUT_nstate_FFd4_2454
    );
  UUT_delay_count_mux0000_0_18 : X_LUT4
    generic map(
      INIT => X"F8F0",
      LOC => "SLICE_X22Y26"
    )
    port map (
      ADR0 => UUT_N45,
      ADR1 => UUT_delay_count_and0000_0,
      ADR2 => UUT_delay_count_mux0000_0_0_0,
      ADR3 => UUT_delay_count_mux0000_0_18_SW0_O,
      O => UUT_delay_count_mux0000_0_18_6824
    );
  UUT_delay_count_mux0000_0_117 : X_LUT4
    generic map(
      INIT => X"CC4C",
      LOC => "SLICE_X18Y28"
    )
    port map (
      ADR0 => UUT_delay_count(2),
      ADR1 => UUT_delay_count(10),
      ADR2 => UUT_delay_count(4),
      ADR3 => UUT_delay_count_mux0000_0_181_O,
      O => UUT_delay_count_mux0000_0_117_6848
    );
  UUT_delay_count_mux0000_0_170 : X_LUT4
    generic map(
      INIT => X"BA30",
      LOC => "SLICE_X23Y29"
    )
    port map (
      ADR0 => UUT_Mtridata_in_i2c_mux0000119_0,
      ADR1 => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_Q,
      ADR2 => UUT_nstate_cmp_eq0012_0,
      ADR3 => UUT_delay_count_mux0000_0_146_O,
      O => UUT_N4
    );
  UUT_delay_count_10 : X_FF
    generic map(
      LOC => "SLICE_X20Y24",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_11_DYMUX_6894,
      CE => VCC,
      CLK => UUT_delay_count_11_CLKINV_6886,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(10)
    );
  UUT_counter_mux0000_4_24 : X_LUT4
    generic map(
      INIT => X"0400",
      LOC => "SLICE_X26Y35"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2450,
      ADR1 => UUT_nstate_FFd2_2446,
      ADR2 => N169,
      ADR3 => UUT_nstate_FFd4_2454,
      O => UUT_counter_mux0000_4_24_8354
    );
  UUT_counter_0 : X_SFF
    generic map(
      LOC => "SLICE_X26Y35",
      INIT => '0'
    )
    port map (
      I => UUT_counter_0_DXMUX_8357,
      CE => VCC,
      CLK => UUT_counter_0_CLKINV_8341,
      SET => GND,
      RST => GND,
      SSET => UUT_counter_0_SRINV_8342,
      SRST => GND,
      O => UUT_counter(0)
    );
  UUT_delay_count_mux0000_0_122 : X_LUT4
    generic map(
      INIT => X"3030",
      LOC => "SLICE_X22Y30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(10),
      ADR2 => UUT_delay_count(2),
      ADR3 => VCC,
      O => UUT_delay_count_mux0000_0_122_8395
    );
  CLK_sI2C_Clk : X_FF
    generic map(
      LOC => "SLICE_X28Y33",
      INIT => '0'
    )
    port map (
      I => CLK_sI2C_Clk_DYMUX_8405,
      CE => CLK_sI2C_Clk_CEINV_8402,
      CLK => CLK_sI2C_Clk_CLKINV_8403,
      SET => GND,
      RST => GND,
      O => CLK_sI2C_Clk_2469
    );
  UUT_out_i2cclk_mux0000118 : X_LUT4
    generic map(
      INIT => X"A0FF",
      LOC => "SLICE_X28Y55"
    )
    port map (
      ADR0 => UUT_ack_count(5),
      ADR1 => VCC,
      ADR2 => UUT_ack_count(1),
      ADR3 => UUT_ack_count(4),
      O => UUT_out_i2cclk_mux0000118_8431
    );
  UUT_out_i2cclk_mux0000162 : X_LUT4
    generic map(
      INIT => X"55CC",
      LOC => "SLICE_X29Y54"
    )
    port map (
      ADR0 => UUT_ack_count(1),
      ADR1 => UUT_ack_count(3),
      ADR2 => VCC,
      ADR3 => UUT_ack_count(2),
      O => UUT_out_i2cclk_mux0000162_8455
    );
  CLK_sI2C_Clk_cmp_eq000017 : X_LUT4
    generic map(
      INIT => X"C0C0",
      LOC => "SLICE_X32Y33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => CLK_sI2C_Clk_cmp_eq00007_0,
      ADR2 => CLK_sI2C_Clk_cmp_eq000016_2684,
      ADR3 => VCC,
      O => CLK_sI2C_Clk_cmp_eq0000
    );
  UUT_delay_count_mux0000_11_2 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X20Y24"
    )
    port map (
      ADR0 => UUT_delay_count_share0000(11),
      ADR1 => UUT_N15_0,
      ADR2 => UUT_delay_count(11),
      ADR3 => UUT_N4_0,
      O => UUT_delay_count_mux0000(11)
    );
  UUT_delay_count_11 : X_FF
    generic map(
      LOC => "SLICE_X20Y24",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_11_DXMUX_6905,
      CE => VCC,
      CLK => UUT_delay_count_11_CLKINV_6886,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(11)
    );
  UUT_delay_count_12 : X_FF
    generic map(
      LOC => "SLICE_X18Y26",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_13_DYMUX_6928,
      CE => VCC,
      CLK => UUT_delay_count_13_CLKINV_6920,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(12)
    );
  UUT_delay_count_mux0000_13_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X18Y26"
    )
    port map (
      ADR0 => UUT_N4_0,
      ADR1 => UUT_N15_0,
      ADR2 => UUT_delay_count_share0000(13),
      ADR3 => UUT_delay_count(13),
      O => UUT_delay_count_mux0000(13)
    );
  UUT_delay_count_13 : X_FF
    generic map(
      LOC => "SLICE_X18Y26",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_13_DXMUX_6939,
      CE => VCC,
      CLK => UUT_delay_count_13_CLKINV_6920,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(13)
    );
  UUT_delay_count_14 : X_FF
    generic map(
      LOC => "SLICE_X20Y27",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_15_DYMUX_6962,
      CE => VCC,
      CLK => UUT_delay_count_15_CLKINV_6954,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(14)
    );
  UUT_delay_count_mux0000_15_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X20Y27"
    )
    port map (
      ADR0 => UUT_delay_count_share0000(15),
      ADR1 => UUT_N15_0,
      ADR2 => UUT_N4_0,
      ADR3 => UUT_delay_count(15),
      O => UUT_delay_count_mux0000(15)
    );
  UUT_delay_count_15 : X_FF
    generic map(
      LOC => "SLICE_X20Y27",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_15_DXMUX_6973,
      CE => VCC,
      CLK => UUT_delay_count_15_CLKINV_6954,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(15)
    );
  UUT_shiftReg_0 : X_SFF
    generic map(
      LOC => "SLICE_X22Y35",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_0_DYMUX_6997,
      CE => VCC,
      CLK => UUT_shiftReg_0_CLKINV_6988,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_0_SRINV_6989,
      SRST => GND,
      O => UUT_shiftReg(0)
    );
  UUT_Mtridata_in_i2c_mux000054 : X_LUT4
    generic map(
      INIT => X"E4E4",
      LOC => "SLICE_X22Y35"
    )
    port map (
      ADR0 => UUT_ClkFallingEdge_2566,
      ADR1 => UUT_Mtridata_in_i2c_2515,
      ADR2 => UUT_shiftReg(0),
      ADR3 => VCC,
      O => UUT_Mtridata_in_i2c_mux000054_7007
    );
  UUT_shiftReg_2 : X_SFF
    generic map(
      LOC => "SLICE_X26Y32",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_2_DYMUX_7030,
      CE => VCC,
      CLK => UUT_shiftReg_2_CLKINV_7021,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_2_SRINV_7022,
      SRST => GND,
      O => UUT_shiftReg(2)
    );
  UUT_shiftReg_mux0000_4_3 : X_LUT4
    generic map(
      INIT => X"8800",
      LOC => "SLICE_X26Y32"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0010,
      ADR1 => UUT_ClkRisingEdge_2465,
      ADR2 => VCC,
      ADR3 => UUT_shiftReg(3),
      O => UUT_shiftReg_mux0000_4_3_7040
    );
  UUT_shiftReg_3 : X_SFF
    generic map(
      LOC => "SLICE_X26Y33",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_3_DYMUX_7059,
      CE => VCC,
      CLK => UUT_shiftReg_3_CLKINV_7050,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_3_SRINV_7051,
      SRST => GND,
      O => UUT_shiftReg(3)
    );
  UUT_N327 : X_LUT4
    generic map(
      INIT => X"5554",
      LOC => "SLICE_X29Y46"
    )
    port map (
      ADR0 => UUT_ack_count(6),
      ADR1 => UUT_ack_count(3),
      ADR2 => UUT_ack_count(0),
      ADR3 => UUT_ack_count(4),
      O => UUT_N327_8146
    );
  UUT_Mtridata_in_i2c_not00012 : X_LUT4
    generic map(
      INIT => X"3200",
      LOC => "SLICE_X26Y49"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => UUT_nstate_FFd1_2447,
      ADR2 => UUT_nstate_FFd4_2454,
      ADR3 => UUT_nstate_FFd3_2450,
      O => UUT_Mtridata_in_i2c_not00012_8170
    );
  UUT_shiftReg_mux0000_2_3 : X_LUT4
    generic map(
      INIT => X"A000",
      LOC => "SLICE_X24Y35"
    )
    port map (
      ADR0 => UUT_shiftReg(1),
      ADR1 => VCC,
      ADR2 => UUT_nstate_cmp_eq0010,
      ADR3 => UUT_ClkRisingEdge_2465,
      O => UUT_shiftReg_mux0000_2_3_8194
    );
  UUT_Mtridata_in_i2c_not000134_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE",
      LOC => "SLICE_X26Y48"
    )
    port map (
      ADR0 => UUT_ack_count(4),
      ADR1 => UUT_ack_count(3),
      ADR2 => UUT_ack_count(5),
      ADR3 => VCC,
      O => N116
    );
  UUT_Dir_mux0000169 : X_LUT4
    generic map(
      INIT => X"CCC4",
      LOC => "SLICE_X23Y30"
    )
    port map (
      ADR0 => UUT_N38_0,
      ADR1 => UUT_nstate_FFd3_2450,
      ADR2 => UUT_Dir_mux0000143_2682,
      ADR3 => UUT_Dir_mux0000148_0,
      O => UUT_Dir_mux0000169_8254
    );
  UUT_Dir_mux00002_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X27Y50"
    )
    port map (
      ADR0 => UUT_ack_count(6),
      ADR1 => UUT_ack_count(7),
      ADR2 => UUT_ack_count(8),
      ADR3 => UUT_ack_count(5),
      O => N22
    );
  UUT_delay_count_mux0000_0_21_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X22Y31"
    )
    port map (
      ADR0 => UUT_delay_count(0),
      ADR1 => UUT_delay_count(1),
      ADR2 => UUT_delay_count(2),
      ADR3 => UUT_delay_count(5),
      O => N71
    );
  UUT_nstate_Out01 : X_LUT4
    generic map(
      INIT => X"0101",
      LOC => "SLICE_X25Y36"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2450,
      ADR1 => UUT_nstate_FFd2_2446,
      ADR2 => UUT_nstate_FFd4_2454,
      ADR3 => VCC,
      O => UUT_nstate_cmp_eq0005
    );
  UUT_writeCount_11 : X_FF
    generic map(
      LOC => "SLICE_X36Y4",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_11_DXMUX_7719,
      CE => VCC,
      CLK => UUT_writeCount_11_CLKINV_7700,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(11)
    );
  UUT_writeCount_12 : X_FF
    generic map(
      LOC => "SLICE_X34Y7",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_13_DYMUX_7742,
      CE => VCC,
      CLK => UUT_writeCount_13_CLKINV_7734,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(12)
    );
  UUT_writeCount_mux0000_13_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X34Y7"
    )
    port map (
      ADR0 => UUT_writeCount(13),
      ADR1 => UUT_N11,
      ADR2 => UUT_N35,
      ADR3 => UUT_writeCount_share0000(13),
      O => UUT_writeCount_mux0000(13)
    );
  UUT_writeCount_13 : X_FF
    generic map(
      LOC => "SLICE_X34Y7",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_13_DXMUX_7753,
      CE => VCC,
      CLK => UUT_writeCount_13_CLKINV_7734,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(13)
    );
  UUT_writeCount_20 : X_FF
    generic map(
      LOC => "SLICE_X36Y9",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_21_DYMUX_7776,
      CE => VCC,
      CLK => UUT_writeCount_21_CLKINV_7768,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(20)
    );
  UUT_writeCount_mux0000_21_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X36Y9"
    )
    port map (
      ADR0 => UUT_writeCount(21),
      ADR1 => UUT_writeCount_share0000(21),
      ADR2 => UUT_N11,
      ADR3 => UUT_N35,
      O => UUT_writeCount_mux0000(21)
    );
  UUT_writeCount_21 : X_FF
    generic map(
      LOC => "SLICE_X36Y9",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_21_DXMUX_7787,
      CE => VCC,
      CLK => UUT_writeCount_21_CLKINV_7768,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(21)
    );
  UUT_writeCount_14 : X_FF
    generic map(
      LOC => "SLICE_X36Y6",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_15_DYMUX_7810,
      CE => VCC,
      CLK => UUT_writeCount_15_CLKINV_7802,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(14)
    );
  UUT_writeCount_mux0000_15_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X36Y6"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(15),
      ADR1 => UUT_N11,
      ADR2 => UUT_writeCount(15),
      ADR3 => UUT_N35,
      O => UUT_writeCount_mux0000(15)
    );
  UUT_writeCount_15 : X_FF
    generic map(
      LOC => "SLICE_X36Y6",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_15_DXMUX_7821,
      CE => VCC,
      CLK => UUT_writeCount_15_CLKINV_7802,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(15)
    );
  UUT_writeCount_22 : X_FF
    generic map(
      LOC => "SLICE_X36Y11",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_23_DYMUX_7844,
      CE => VCC,
      CLK => UUT_writeCount_23_CLKINV_7836,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(22)
    );
  UUT_writeCount_mux0000_23_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X36Y11"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(23),
      ADR1 => UUT_writeCount(23),
      ADR2 => UUT_N11,
      ADR3 => UUT_N35,
      O => UUT_writeCount_mux0000(23)
    );
  UUT_writeCount_23 : X_FF
    generic map(
      LOC => "SLICE_X36Y11",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_23_DXMUX_7855,
      CE => VCC,
      CLK => UUT_writeCount_23_CLKINV_7836,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(23)
    );
  UUT_writeCount_16 : X_FF
    generic map(
      LOC => "SLICE_X36Y8",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_17_DYMUX_7878,
      CE => VCC,
      CLK => UUT_writeCount_17_CLKINV_7870,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(16)
    );
  UUT_writeCount_mux0000_17_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X36Y8"
    )
    port map (
      ADR0 => UUT_N35,
      ADR1 => UUT_writeCount_share0000(17),
      ADR2 => UUT_N11,
      ADR3 => UUT_writeCount(17),
      O => UUT_writeCount_mux0000(17)
    );
  UUT_writeCount_17 : X_FF
    generic map(
      LOC => "SLICE_X36Y8",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_17_DXMUX_7889,
      CE => VCC,
      CLK => UUT_writeCount_17_CLKINV_7870,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(17)
    );
  UUT_writeCount_24 : X_FF
    generic map(
      LOC => "SLICE_X36Y13",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_25_DYMUX_7912,
      CE => VCC,
      CLK => UUT_writeCount_25_CLKINV_7904,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(24)
    );
  UUT_writeCount_mux0000_25_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X36Y13"
    )
    port map (
      ADR0 => UUT_N35,
      ADR1 => UUT_writeCount_share0000(25),
      ADR2 => UUT_N11,
      ADR3 => UUT_writeCount(25),
      O => UUT_writeCount_mux0000(25)
    );
  UUT_writeCount_25 : X_FF
    generic map(
      LOC => "SLICE_X36Y13",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_25_DXMUX_7923,
      CE => VCC,
      CLK => UUT_writeCount_25_CLKINV_7904,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(25)
    );
  UUT_writeCount_18 : X_FF
    generic map(
      LOC => "SLICE_X36Y7",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_19_DYMUX_7946,
      CE => VCC,
      CLK => UUT_writeCount_19_CLKINV_7938,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(18)
    );
  UUT_writeCount_mux0000_19_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X36Y7"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(19),
      ADR1 => UUT_writeCount(19),
      ADR2 => UUT_N35,
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(19)
    );
  UUT_writeCount_19 : X_FF
    generic map(
      LOC => "SLICE_X36Y7",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_19_DXMUX_7957,
      CE => VCC,
      CLK => UUT_writeCount_19_CLKINV_7938,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(19)
    );
  UUT_writeCount_26 : X_FF
    generic map(
      LOC => "SLICE_X36Y12",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_27_DYMUX_7980,
      CE => VCC,
      CLK => UUT_writeCount_27_CLKINV_7972,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(26)
    );
  UUT_writeCount_mux0000_27_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X36Y12"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(27),
      ADR1 => UUT_writeCount(27),
      ADR2 => UUT_N11,
      ADR3 => UUT_N35,
      O => UUT_writeCount_mux0000(27)
    );
  UUT_writeCount_27 : X_FF
    generic map(
      LOC => "SLICE_X36Y12",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_27_DXMUX_7991,
      CE => VCC,
      CLK => UUT_writeCount_27_CLKINV_7972,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(27)
    );
  UUT_writeCount_28 : X_FF
    generic map(
      LOC => "SLICE_X36Y14",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_29_DYMUX_8014,
      CE => VCC,
      CLK => UUT_writeCount_29_CLKINV_8006,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(28)
    );
  UUT_writeCount_mux0000_29_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X36Y14"
    )
    port map (
      ADR0 => UUT_writeCount(29),
      ADR1 => UUT_writeCount_share0000(29),
      ADR2 => UUT_N35,
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(29)
    );
  UUT_writeCount_29 : X_FF
    generic map(
      LOC => "SLICE_X36Y14",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_29_DXMUX_8025,
      CE => VCC,
      CLK => UUT_writeCount_29_CLKINV_8006,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(29)
    );
  UUT_Mtridata_in_i2c_mux0000119 : X_LUT4
    generic map(
      INIT => X"C8C8",
      LOC => "SLICE_X26Y29"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => UUT_nstate_FFd3_2450,
      ADR2 => UUT_nstate_FFd4_2454,
      ADR3 => VCC,
      O => UUT_Mtridata_in_i2c_mux0000119_8050
    );
  UUT_shiftReg_mux0000_0_25 : X_LUT4
    generic map(
      INIT => X"A2A2",
      LOC => "SLICE_X22Y34"
    )
    port map (
      ADR0 => UUT_ClkFallingEdge_2566,
      ADR1 => UUT_shiftReg_and0000_0,
      ADR2 => UUT_shiftReg_or0000,
      ADR3 => VCC,
      O => UUT_shiftReg_mux0000_0_25_8074
    );
  UUT_out_i2cclk_mux0000131 : X_LUT4
    generic map(
      INIT => X"EEEF",
      LOC => "SLICE_X27Y47"
    )
    port map (
      ADR0 => UUT_ack_count(8),
      ADR1 => UUT_ack_count(0),
      ADR2 => UUT_ack_count(7),
      ADR3 => UUT_ack_count(5),
      O => UUT_out_i2cclk_mux0000131_8098
    );
  UUT_in_i2cLogicTrst1 : X_LUT4
    generic map(
      INIT => X"FFCC",
      LOC => "SLICE_X23Y38"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_Mtridata_in_i2c_2515,
      ADR2 => VCC,
      ADR3 => UUT_Mtrien_in_i2c_2614,
      O => UUT_in_i2c
    );
  UUT_ClkEdge_0 : X_FF
    generic map(
      LOC => "SLICE_X27Y33",
      INIT => '0'
    )
    port map (
      I => UUT_ClkEdge_1_DYMUX_8501,
      CE => VCC,
      CLK => UUT_ClkEdge_1_CLKINV_8499,
      SET => GND,
      RST => GND,
      O => UUT_ClkEdge(0)
    );
  UUT_ClkEdge_1 : X_FF
    generic map(
      LOC => "SLICE_X27Y33",
      INIT => '0'
    )
    port map (
      I => UUT_ClkEdge_1_DXMUX_8506,
      CE => VCC,
      CLK => UUT_ClkEdge_1_CLKINV_8499,
      SET => GND,
      RST => GND,
      O => UUT_ClkEdge(1)
    );
  UUT_Dir_mux000082 : X_LUT4
    generic map(
      INIT => X"0080",
      LOC => "SLICE_X23Y35"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2450,
      ADR1 => UUT_shiftReg_cmp_eq0002_0,
      ADR2 => UUT_N38_0,
      ADR3 => N183,
      O => UUT_Dir_mux000082_8531
    );
  UUT_nstate_Out11 : X_LUT4
    generic map(
      INIT => X"000C",
      LOC => "SLICE_X26Y45"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_nstate_FFd4_2454,
      ADR2 => UUT_nstate_FFd2_2446,
      ADR3 => UUT_nstate_FFd3_2450,
      O => UUT_nstate_cmp_eq0006
    );
  UUT_shiftReg_mux0000_0_111_SW0 : X_LUT4
    generic map(
      INIT => X"FF7F",
      LOC => "SLICE_X25Y28"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => UUT_nstate_FFd4_2454,
      ADR2 => UUT_nstate_FFd3_2450,
      ADR3 => UUT_ClkFallingEdge_2566,
      O => N123
    );
  UUT_nstate_Out71 : X_LUT4
    generic map(
      INIT => X"0030",
      LOC => "SLICE_X25Y29"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_nstate_FFd4_2454,
      ADR2 => UUT_nstate_FFd3_2450,
      ADR3 => UUT_nstate_FFd2_2446,
      O => UUT_nstate_cmp_eq0012
    );
  UUT_shiftReg_mux0000_0_244_SW0 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X24Y29"
    )
    port map (
      ADR0 => UUT_shiftReg(4),
      ADR1 => UUT_shiftReg(6),
      ADR2 => UUT_shiftReg_mux0000_0_240_2471,
      ADR3 => UUT_N62_0,
      O => N102
    );
  UUT_nstate_FFd1_1 : X_SFF
    generic map(
      LOC => "SLICE_X26Y39",
      INIT => '0'
    )
    port map (
      I => UUT_nstate_FFd1_1_DYMUX_8661,
      CE => VCC,
      CLK => UUT_nstate_FFd1_1_CLKINV_8658,
      SET => GND,
      RST => GND,
      SSET => UUT_nstate_FFd1_1_SRINV_8659,
      SRST => GND,
      O => UUT_nstate_FFd1_1_2596
    );
  UUT_nstate_FFd2_1 : X_SFF
    generic map(
      LOC => "SLICE_X27Y39",
      INIT => '0'
    )
    port map (
      I => UUT_nstate_FFd2_1_DYMUX_8673,
      CE => VCC,
      CLK => UUT_nstate_FFd2_1_CLKINV_8670,
      SET => GND,
      RST => GND,
      SSET => UUT_nstate_FFd2_1_SRINV_8671,
      SRST => GND,
      O => UUT_nstate_FFd2_1_2599
    );
  UUT_nstate_FFd3_1 : X_FF
    generic map(
      LOC => "SLICE_X25Y40",
      INIT => '0'
    )
    port map (
      I => UUT_nstate_FFd3_1_DYMUX_8683,
      CE => VCC,
      CLK => UUT_nstate_FFd3_1_CLKINV_8681,
      SET => GND,
      RST => GND,
      O => UUT_nstate_FFd3_1_2598
    );
  UUT_nstate_FFd4_1 : X_SFF
    generic map(
      LOC => "SLICE_X24Y41",
      INIT => '0'
    )
    port map (
      I => UUT_nstate_FFd4_1_DYMUX_8694,
      CE => VCC,
      CLK => UUT_nstate_FFd4_1_CLKINV_8691,
      SET => GND,
      RST => GND,
      SSET => UUT_nstate_FFd4_1_SRINV_8692,
      SRST => GND,
      O => UUT_nstate_FFd4_1_2597
    );
  UUT_pstate_mux0000_6_SW0 : X_LUT4
    generic map(
      INIT => X"FFBF",
      LOC => "SLICE_X26Y46"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2446,
      ADR1 => UUT_nstate_FFd4_2454,
      ADR2 => UUT_nstate_FFd3_2450,
      ADR3 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      O => N39
    );
  UUT_pstate_mux0000_5_SW0 : X_LUT4
    generic map(
      INIT => X"0040",
      LOC => "SLICE_X22Y38"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2454,
      ADR1 => UUT_nstate_FFd2_2446,
      ADR2 => UUT_nstate_FFd3_2450,
      ADR3 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      O => N42
    );
  UUT_ClkFallingEdge : X_SFF
    generic map(
      LOC => "SLICE_X27Y31",
      INIT => '0'
    )
    port map (
      I => UUT_ClkFallingEdge_DYMUX_8754,
      CE => VCC,
      CLK => UUT_ClkFallingEdge_CLKINV_8751,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => UUT_ClkFallingEdge_SRINV_8752,
      O => UUT_ClkFallingEdge_2566
    );
  UUT_Mtridata_in_i2c_not000134_SW2 : X_LUT4
    generic map(
      INIT => X"BFFE",
      LOC => "SLICE_X27Y52"
    )
    port map (
      ADR0 => UUT_ack_count(1),
      ADR1 => UUT_ack_count(4),
      ADR2 => UUT_ack_count(5),
      ADR3 => UUT_ack_count(3),
      O => N126
    );
  UUT_Mtridata_in_i2c_not0001125_SW0 : X_LUT4
    generic map(
      INIT => X"FFBF",
      LOC => "SLICE_X26Y47"
    )
    port map (
      ADR0 => UUT_ack_count(3),
      ADR1 => UUT_nstate_FFd4_2454,
      ADR2 => UUT_Mtridata_in_i2c_not000181,
      ADR3 => UUT_ack_count(6),
      O => N157
    );
  UUT_shiftReg_mux0000_0_130_SW1 : X_LUT4
    generic map(
      INIT => X"CC44",
      LOC => "SLICE_X26Y31"
    )
    port map (
      ADR0 => UUT_ClkFallingEdge_2566,
      ADR1 => UUT_shiftReg(7),
      ADR2 => VCC,
      ADR3 => UUT_shiftReg_mux0000_0_110_0,
      O => N78
    );
  GLOBAL_LOGIC0_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  GLOBAL_LOGIC1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  UUT_ack_count_share0000_8_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X37Y63"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_ack_count_share0000_8_F
    );
  UUT_ack_count_share0000_8_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X37Y63"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_ack_count(9),
      O => UUT_ack_count_share0000_8_G
    );
  UUT_ack_count_share0000_10_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X37Y64"
    )
    port map (
      ADR0 => UUT_ack_count(10),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_ack_count_share0000_10_F
    );
  UUT_delay_count_share0000_0_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X21Y20"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(1),
      O => UUT_delay_count_share0000_0_G
    );
  UUT_delay_count_share0000_2_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X21Y21"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_share0000_2_F
    );
  UUT_delay_count_share0000_2_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X21Y21"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(3),
      O => UUT_delay_count_share0000_2_G
    );
  UUT_writeCount_share0000_28_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X37Y14"
    )
    port map (
      ADR0 => UUT_writeCount(28),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_28_F
    );
  UUT_writeCount_share0000_28_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X37Y14"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(29),
      O => UUT_writeCount_share0000_28_G
    );
  UUT_ack_count_share0000_0_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X37Y59"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_ack_count_share0000_0_G
    );
  UUT_ack_count_share0000_2_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X37Y60"
    )
    port map (
      ADR0 => UUT_ack_count(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_ack_count_share0000_2_F
    );
  UUT_ack_count_share0000_2_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X37Y60"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_ack_count(3),
      ADR3 => VCC,
      O => UUT_ack_count_share0000_2_G
    );
  UUT_ack_count_share0000_4_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X37Y61"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_ack_count_share0000_4_F
    );
  UUT_ack_count_share0000_4_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X37Y61"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_ack_count(5),
      O => UUT_ack_count_share0000_4_G
    );
  UUT_ack_count_share0000_6_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X37Y62"
    )
    port map (
      ADR0 => UUT_ack_count(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_ack_count_share0000_6_F
    );
  UUT_ack_count_share0000_6_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X37Y62"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_ack_count(7),
      ADR3 => VCC,
      O => UUT_ack_count_share0000_6_G
    );
  UUT_writeCount_share0000_10_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X37Y5"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(10),
      O => UUT_writeCount_share0000_10_F
    );
  UUT_writeCount_share0000_10_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X37Y5"
    )
    port map (
      ADR0 => UUT_writeCount(11),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_10_G
    );
  UUT_writeCount_share0000_12_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X37Y6"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(12),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_12_F
    );
  UUT_writeCount_share0000_12_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X37Y6"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(13),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_12_G
    );
  UUT_writeCount_share0000_14_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X37Y7"
    )
    port map (
      ADR0 => UUT_writeCount(14),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_14_F
    );
  UUT_writeCount_share0000_14_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X37Y7"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(15),
      O => UUT_writeCount_share0000_14_G
    );
  UUT_writeCount_share0000_16_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X37Y8"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(16),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_16_F
    );
  UUT_writeCount_share0000_16_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X37Y8"
    )
    port map (
      ADR0 => UUT_writeCount(17),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_16_G
    );
  UUT_writeCount_share0000_18_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X37Y9"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(18),
      O => UUT_writeCount_share0000_18_F
    );
  UUT_writeCount_share0000_18_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X37Y9"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(19),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_18_G
    );
  UUT_writeCount_share0000_20_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X37Y10"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(20),
      O => UUT_writeCount_share0000_20_F
    );
  UUT_writeCount_share0000_20_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X37Y10"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(21),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_20_G
    );
  UUT_writeCount_share0000_22_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X37Y11"
    )
    port map (
      ADR0 => UUT_writeCount(22),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_22_F
    );
  UUT_writeCount_share0000_22_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X37Y11"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(23),
      O => UUT_writeCount_share0000_22_G
    );
  UUT_writeCount_share0000_24_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X37Y12"
    )
    port map (
      ADR0 => UUT_writeCount(24),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_24_F
    );
  UUT_writeCount_share0000_24_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X37Y12"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(25),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_24_G
    );
  UUT_writeCount_share0000_26_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X37Y13"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(26),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_26_F
    );
  UUT_writeCount_share0000_26_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X37Y13"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(27),
      O => UUT_writeCount_share0000_26_G
    );
  UUT_writeCount_share0000_0_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X37Y0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(1),
      O => UUT_writeCount_share0000_0_G
    );
  UUT_writeCount_share0000_2_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X37Y1"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(2),
      O => UUT_writeCount_share0000_2_F
    );
  UUT_writeCount_share0000_2_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X37Y1"
    )
    port map (
      ADR0 => UUT_writeCount(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_2_G
    );
  UUT_writeCount_share0000_4_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X37Y2"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_4_F
    );
  UUT_writeCount_share0000_4_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X37Y2"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(5),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_4_G
    );
  UUT_writeCount_share0000_6_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X37Y3"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(6),
      O => UUT_writeCount_share0000_6_F
    );
  UUT_writeCount_share0000_6_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X37Y3"
    )
    port map (
      ADR0 => UUT_writeCount(7),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_6_G
    );
  UUT_writeCount_share0000_8_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X37Y4"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_8_F
    );
  UUT_writeCount_share0000_8_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X37Y4"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(9),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_8_G
    );
  CLK_clk_div_0_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X33Y32"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => CLK_clk_div(1),
      ADR3 => VCC,
      O => CLK_clk_div_0_G
    );
  CLK_clk_div_2_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X33Y33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => CLK_clk_div(2),
      O => CLK_clk_div_2_F
    );
  CLK_clk_div_2_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X33Y33"
    )
    port map (
      ADR0 => CLK_clk_div(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CLK_clk_div_2_G
    );
  CLK_clk_div_4_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X33Y34"
    )
    port map (
      ADR0 => CLK_clk_div(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CLK_clk_div_4_F
    );
  CLK_clk_div_4_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X33Y34"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => CLK_clk_div(5),
      O => CLK_clk_div_4_G
    );
  CLK_clk_div_6_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X33Y35"
    )
    port map (
      ADR0 => VCC,
      ADR1 => CLK_clk_div(6),
      ADR2 => VCC,
      ADR3 => VCC,
      O => CLK_clk_div_6_F
    );
  UUT_delay_count_share0000_4_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X21Y22"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_share0000_4_F
    );
  UUT_delay_count_share0000_4_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X21Y22"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(5),
      O => UUT_delay_count_share0000_4_G
    );
  UUT_delay_count_share0000_6_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X21Y23"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(6),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_share0000_6_F
    );
  UUT_delay_count_share0000_6_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X21Y23"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(7),
      O => UUT_delay_count_share0000_6_G
    );
  UUT_delay_count_share0000_8_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X21Y24"
    )
    port map (
      ADR0 => UUT_delay_count(8),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_share0000_8_F
    );
  UUT_delay_count_share0000_8_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X21Y24"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_share0000_8_G
    );
  UUT_delay_count_share0000_10_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X21Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(10),
      ADR3 => VCC,
      O => UUT_delay_count_share0000_10_F
    );
  UUT_delay_count_share0000_10_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X21Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(11),
      O => UUT_delay_count_share0000_10_G
    );
  UUT_delay_count_share0000_12_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X21Y26"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(12),
      O => UUT_delay_count_share0000_12_F
    );
  UUT_delay_count_share0000_12_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X21Y26"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(13),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_share0000_12_G
    );
  UUT_delay_count_share0000_14_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X21Y27"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(14),
      O => UUT_delay_count_share0000_14_F
    );
  I2C_Data_OUTPUT_TFF_TMUX : X_BUF
    generic map(
      LOC => "PAD18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_2438,
      O => I2C_Data_T
    );
  I2C_Data_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c,
      O => I2C_Data_O
    );
  I2C_Clk_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_2445,
      O => I2C_Clk_O
    );
  NlwBlock_I2CmasterDemo_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_I2CmasterDemo_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

